VHDL-Stopwatch

Implemeted a functional stopwatch in VHDL with the start/pause/reset functionality by clock divider by programming Basys-3 FPGA Boards.

Name		Name	Last commit message	Last commit date
Latest commit History 4 Commits
README.md		README.md
Stopwatch_report.pdf		Stopwatch_report.pdf
VHDL Stopwatch.pdf		VHDL Stopwatch.pdf
basys3.xdc		basys3.xdc
counter.vhd		counter.vhd
counter_2.vhd		counter_2.vhd
multiplexer.vhd		multiplexer.vhd
segment.vhd		segment.vhd
stopwatch.bit		stopwatch.bit
stopwatch.vhd		stopwatch.vhd
stopwatch_utilization_synth.rpt		stopwatch_utilization_synth.rpt
testbench2.vhd		testbench2.vhd
timingcircuit.vhd		timingcircuit.vhd

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