-
Notifications
You must be signed in to change notification settings - Fork 0
/
Copy pathequalizer_system_m.vhd
153 lines (137 loc) · 3.52 KB
/
equalizer_system_m.vhd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
--Sistema de ecualizacion completo con mejoras añadidas
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity equalizer_system_m is
generic (
reverb_size : integer := 256;
reverb_gain : integer := 100
);
port (
sin : in signed (15 downto 0);
sout : out signed (15 downto 0);
clk : in bit;
f_sel : in unsigned (2 downto 0);
g_sel : in unsigned (3 downto 0);
g_en : in bit;
rev_en : in bit;
level0 : out unsigned (7 downto 0);
level1 : out unsigned (7 downto 0);
level2 : out unsigned (7 downto 0);
level3 : out unsigned (7 downto 0);
level4 : out unsigned (7 downto 0);
level5 : out unsigned (7 downto 0);
level6 : out unsigned (7 downto 0)
);
end equalizer_system_m;
architecture whole of equalizer_system_m is
signal f0_out : signed (15 downto 0) := to_signed(0,16);
signal f1_out : signed (15 downto 0) := to_signed(0,16);
signal f2_out : signed (15 downto 0) := to_signed(0,16);
signal f3_out : signed (15 downto 0) := to_signed(0,16);
signal f4_out : signed (15 downto 0) := to_signed(0,16);
signal f5_out : signed (15 downto 0) := to_signed(0,16);
signal f6_out : signed (15 downto 0) := to_signed(0,16);
signal fb_out : signed (15 downto 0) := to_signed(0,16);
signal rv_out : signed (15 downto 0) := to_signed(0,16);
signal fb_in : signed (15 downto 0) := to_signed(0,16);
component filter_bench_m is
port (
sin : in signed (15 downto 0);
clk : in bit;
f_sel : in unsigned (2 downto 0);
g_sel : in unsigned (3 downto 0);
g_en : in bit;
sout : out signed (15 downto 0);
sout0 : out signed (15 downto 0);
sout1 : out signed (15 downto 0);
sout2 : out signed (15 downto 0);
sout3 : out signed (15 downto 0);
sout4 : out signed (15 downto 0);
sout5 : out signed (15 downto 0);
sout6 : out signed (15 downto 0)
);
end component;
component reverb_m is
generic (
size: integer := 256;
gain: integer := 100
);
port (
enable : in bit;
clk : in bit;
dataout : out signed(15 downto 0);
datain : in signed(15 downto 0)
);
end component;
component vumetro is
generic (
defhold : integer := 500 --Ciclos de reloj que se mantendran los picos
);
port (
clk : in bit;
sin0 : in signed(15 downto 0);
sin1 : in signed(15 downto 0);
sin2 : in signed(15 downto 0);
sin3 : in signed(15 downto 0);
sin4 : in signed(15 downto 0);
sin5 : in signed(15 downto 0);
sin6 : in signed(15 downto 0);
out0 : out unsigned(7 downto 0);
out1 : out unsigned(7 downto 0);
out2 : out unsigned(7 downto 0);
out3 : out unsigned(7 downto 0);
out4 : out unsigned(7 downto 0);
out5 : out unsigned(7 downto 0);
out6 : out unsigned(7 downto 0)
);
end component;
begin
fb_in <= rv_out + sin;
sout <= fb_out;
reverb0 : reverb_m
GENERIC MAP (
size => reverb_size,
gain => reverb_gain)
PORT MAP (
enable => rev_en,
datain => fb_out,
dataout => rv_out,
clk => clk);
fbench0 : filter_bench_m
PORT MAP (
sin => fb_in,
clk => clk,
f_sel => f_sel,
g_sel => g_sel,
g_en => g_en,
sout => fb_out,
sout0 => f0_out,
sout1 => f1_out,
sout2 => f2_out,
sout3 => f3_out,
sout4 => f4_out,
sout5 => f5_out,
sout6 => f6_out
);
vumetro0 : vumetro
GENERIC MAP (
defhold => 500)
PORT MAP (
clk => clk,
sin0 => f0_out,
sin1 => f1_out,
sin2 => f2_out,
sin3 => f3_out,
sin4 => f4_out,
sin5 => f5_out,
sin6 => f6_out,
out0 => level0,
out1 => level1,
out2 => level2,
out3 => level3,
out4 => level4,
out5 => level5,
out6 => level6
);
end whole;