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CPU and Pipeline

risc-v core-code

Pipline:

  • IF: Instruction Fetch
  • EX: Execution
  • WB: Write Back

Supported Instructions

ADD rd, rs1, rs2
ADDI rd, rs1, imm
SUB rd, rs1, rs2

JAL rd, imm

FLD rd, imm(rs1) : rd <- MEM[rs1+imm]
FSD rs2, imm(rs1) : MEM[rs1+imm] <- rs2

FADD rd, rs1, rs2
FSUB rd, rs1, rs2
FMUL rd, rs1, rs2
FDIV rd, rs1, rs2

Reference