Direct pipeline VHDL/Verilog modules?

[bartokon]

Would it be possible to write bare VHDL/Verilog code and automatically pipeline it?
What would happen if I just copied and pasted VHDL code to pipelineC function? That VHDL code would be pipelined?
https://link.springer.com/chapter/10.1007/978-3-662-49674-9_38

[JulianKemmerer]

Excellent question - quick summary of existing behavior in this area:
https://github.com/JulianKemmerer/PipelineC/wiki/Raw-HDL-Insertion

Which does

uint64_t main(uint64_t x, uint64_t y) 
{
__vhdl__("\
  -- Arch declarations go here \n\
  begin \n\
  -- The arch body, processes, assignments, etc go here \n\
  return_output <= x + y; \n\
");
}

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.c_structs_pkg.all;
entity main_0CLK_d751 is
port(
 clk : in std_logic;
 x : in unsigned(63 downto 0);
 y : in unsigned(63 downto 0);
 return_output : out unsigned(63 downto 0));
end main_0CLK_d751;
architecture arch of main_0CLK_d751 is
  -- Arch declarations go here 
  begin 
  -- The arch body, processes, assignments, etc go here 
  return_output <= x + y; 
end arch;

But per your question @bartokon , these will not be pipelined automatically. ~ Comes from a place of essentially dropping in the blob of text the user wrote. the user can write whatever VHDL string they want there... and I am not analyzing their VHDL... so its like 'how do you pipeline this arbitrary vhdl text?' which isnt workable...

But how can we make this work? 🤓 hm....

[JulianKemmerer]

How about this kind of thinking

The user gives a function signature of something raw vhdl that they have pipelined by hand

#pragma FUNC_MANUAL_PIPELINE my_custom_pipeline
int32_t my_custom_pipeline(int32_t a, int32_t b)
{
  // NOTHING GOES HERE
}

And then they define - what does the custom pipelining of my VHDL (or C) look like ... they specify the implementation for 1 stage, 2 stage, etc as needed

// Version to use for 1 comb. logic stage, 0 regs
#pragma FUNC_PIPELINE_LATENCY my_custom_pipeline 0
int32_t my_custom_pipeline_0clk(int32_t a, int32_t b)
{
  /*
  Anything can be here - C code, or raw VHDL
  As long as it is your functionality in as comb. logic
  */
}

// Version that splits comb logic into 2 cycles, 1 clk latency
#pragma FUNC_PIPELINE_LATENCY my_custom_pipeline 1
int32_t my_custom_pipeline_1clk(int32_t a, int32_t b)
{
  /*
  Anything can be here - C code, or raw VHDL
  As long as it is your functionality in 1 clock cycle latency
  */
}

// Version that splits comb logic into 3 cycles, 2 clk latency
#pragma FUNC_PIPELINE_LATENCY my_custom_pipeline 2
int32_t my_custom_pipeline_2clk(int32_t a, int32_t b)
{
  /*
  Anything can be here - C code, or raw VHDL
  As long as it is your functionality in 2 clock cycles latency
  */
}

Could maybe rig up something weird where the Anything can be here - C code, or raw VHDL maybe expects some LATENCY constant in code - and the VHDL/C uses that ~generic value to generate code in one module (as opposed a module/definition for 1 clk, another for 2 clks, etc)

[JulianKemmerer]

Something I've really considered lately, especially for those people who will not switch to a primarily-other-HDL-language environment - they are always going to be VHDL/Verilog first/primarily/wrapping any generated code.

What if we could tag a chunk of comb. logic from HDL (i.e. a function) and then somehow make it get autopipelined and be easily usable right in the HDL?

Ex.

-- VHDL user attributes sound nice for this?
attribute AUTO_PIPELINE: boolean;
attribute AUTO_PIPELINE of function my_pipelinec_func is true;
function my_pipelinec_func(a : signed(31 downto 0); b : unsigned(31 downto 0)) return signed(31 downto 0) is
begin
  return a + b;
end function;

Somehow we parse the HDL 😬 ... and get the same kind of dataflow info from the HDL func as we would have gotten from parsing C code ...?

And generate my_pipelinec_func_33clk or whatever to meet some timing goal idk

Seems like alot to ask for to parse the HDL function def... hmmm

🕶️ would be HACK AF but along the lines of What would happen if I just copied and pasted VHDL code to pipelineC function

Consider the above example - without parsing/understanding the HDL text return a+b; is also valid C/PipelineC ...

If you imposed some rules on the VHDL function syntax you can use - and hacky replaced like VHDL := with C =, etc - you should essentially have the same functionality 😁