optimized leading zero counter #39
suarezvictor
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Comparing #pragma MAIN_MHZ new_count0s 1.0
uint6_t new_count0s(uint32_t a32)
{
uint16_t a16;
uint8_t a8;
uint4_t a4;
uint2_t a2;
uint2_t a1;
uint1_t b16 = (a32 >> 16) == 0; a16 = b16 ? (a32 >> 0) : a32 >> 16;
uint1_t b8 = (a16 >> 8) == 0; a8 = b8 ? (a16 >> 0) : a16 >> 8;
uint1_t b4 = ( a8 >> 4) == 0; a4 = b4 ? ( a8 >> 0) : a8 >> 4;
uint1_t b2 = ( a4 >> 2) == 0; a2 = b2 ? ( a4 >> 0) : a4 >> 2;
uint1_t b1 = ( a2 >> 1) == 0; a1 = b1 ? ( a2 >> 0) : a2 >> 1;
uint5_t r = (b16 << 4) | (b8 << 3) | (b4 << 2) | (b2 << 1) | b1;
return (r == 31 & a1 == 0) ? (uint6_t)32 : (uint6_t)r;
}
#pragma MAIN_MHZ orig_count0s 1.0
uint6_t orig_count0s(uint32_t a32)
{
return count0s_uint32(a32);
} new_count0s BAD NVM
orig_count0s
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Damn nvm need to add casting like so uint5_t r = ((uint5_t)b16 << 4) | ((uint4_t)b8 << 3) | ((uint3_t)b4 << 2) | ((uint2_t)b2 << 1) | (uint1_t)b1; new_count0s
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I think the workflow should be allways as this:
1-compile with a regular compiler and test (1 second)
2-pipelinec it, verilate, test
3-do synth
This way you can catch errors. An interesting thing here is how a pass with
a C compiler gives different results than with pipelineC. Doesn't seem good.
Maybe at least pipelineC should know such bit operations are different than
with C and give a warning or error.
El mar., 26 oct. 2021 20:59, Julian Kemmerer ***@***.***>
escribió:
… Damn nvm
There was issue with bit widths
need to add casting like so
uint5_t r = ((uint5_t)b16 << 4) | ((uint4_t)b8 << 3) | ((uint3_t)b4 << 2) | ((uint2_t)b2 << 1) | (uint1_t)b1;
+------+-----+------+
| |Cell |Count |
+------+-----+------+
|1 |LUT2 | 6|
|2 |LUT4 | 10|
|3 |LUT5 | 6|
|4 |LUT6 | 17|
|5 |FDRE | 38|
+------+-----+------+
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Implementation of leading zero counter without adders (only muxes and AND/OR gates)
Return is uint6_t (a zero value has 32-bit leading zeros)
tested 10 million times with random values and (1 << random) values for including the zero
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