From eea3b7331533238e7ff89885606b2ccbb45f6419 Mon Sep 17 00:00:00 2001 From: Jeremy Grosser Date: Fri, 15 Nov 2024 13:15:33 -0800 Subject: [PATCH] Enable coprocessors, rewrite RP2350 startup, read full I2C status register --- src/devices/rp2350/rp-clock.adb | 408 ++++++++++---------------------- src/drivers/rp-clock.ads | 6 +- src/drivers/rp-i2c_master.adb | 11 +- src/startup/rp2350/crt0.S | 24 +- tests/alire.toml | 6 +- 5 files changed, 152 insertions(+), 303 deletions(-) diff --git a/src/devices/rp2350/rp-clock.adb b/src/devices/rp2350/rp-clock.adb index cb1627e..615d27d 100644 --- a/src/devices/rp2350/rp-clock.adb +++ b/src/devices/rp2350/rp-clock.adb @@ -3,7 +3,6 @@ -- -- SPDX-License-Identifier: BSD-3-Clause -- -with Ada.Unchecked_Conversion; with RP2350_SVD.CLOCKS; use RP2350_SVD.CLOCKS; with RP2040_SVD.PLL; use RP2040_SVD.PLL; with RP2350_SVD.XOSC; @@ -11,183 +10,6 @@ with RP2350_SVD.ROSC; with RP.Reset; package body RP.Clock is - procedure Enable_ROSC; - - procedure Enable_XOSC; - - -- Table 543. CLK_GPOUT0_CTRL Register - type CLK_CTRL_AUXSRC_Field is - (PLL_SYS, GPIN0, GPIN1, PLL_USB, PLL_USB_PRIMARY_REF_OPCG, ROSC, XOSC, - LPOSC, SYS, USB, ADC, REF, PERI, HSTX, OTP_CLK2FC) - with Size => 4; - for CLK_CTRL_AUXSRC_Field use - (PLL_SYS => 0, - GPIN0 => 1, - GPIN1 => 2, - PLL_USB => 3, - PLL_USB_PRIMARY_REF_OPCG => 4, - ROSC => 5, - XOSC => 6, - LPOSC => 7, - SYS => 8, - USB => 9, - ADC => 10, - REF => 11, - PERI => 12, - HSTX => 13, - OTP_CLK2FC => 14); - - -- SRC can only be set for REF and SYS and has different meanings for both - subtype CLK_CTRL_SRC_Field is UInt2; - REF_SRC_ROSC : constant CLK_CTRL_SRC_Field := 0; - -- REF_SRC_AUX : constant CLK_CTRL_SRC_Field := 1; - REF_SRC_XOSC : constant CLK_CTRL_SRC_Field := 2; - -- REF_SRC_LPOSC : constant CLK_CTRL_SRC_Field := 3; - - SYS_SRC_REF : constant CLK_CTRL_SRC_Field := 0; - SYS_SRC_AUX : constant CLK_CTRL_SRC_Field := 1; - - USB_SRC_USB : constant CLK_CTRL_SRC_Field := 0; - ADC_SRC_USB : constant CLK_CTRL_SRC_Field := 0; - PERI_SRC_SYS : constant CLK_CTRL_SRC_Field := 0; - - subtype CLK_CTRL_PHASE_Field is UInt2; - - type CLK_CTRL_Register is record - AUXSRC : CLK_CTRL_AUXSRC_Field := PLL_SYS; - SRC : CLK_CTRL_SRC_Field := 0; - KILL : Boolean := False; - ENABLE : Boolean := False; - DC50 : Boolean := False; - PHASE : CLK_CTRL_PHASE_Field := 0; - NUDGE : Boolean := False; - end record - with Volatile_Full_Access, Object_Size => 32; - for CLK_CTRL_Register use record - SRC at 0 range 0 .. 1; - AUXSRC at 0 range 5 .. 8; - KILL at 0 range 10 .. 10; - ENABLE at 0 range 11 .. 11; - DC50 at 0 range 12 .. 12; - PHASE at 0 range 16 .. 17; - NUDGE at 0 range 20 .. 20; - end record; - - subtype CLK_DIV_INT_Field is UInt24; - subtype CLK_DIV_FRAC_Field is UInt8; - - type CLK_DIV_Register is record - INT : CLK_DIV_INT_Field := 1; - FRAC : CLK_DIV_FRAC_Field := 0; - end record - with Volatile_Full_Access, Object_Size => 32; - for CLK_DIV_Register use record - INT at 0 range 8 .. 31; - FRAC at 0 range 0 .. 7; - end record; - - function To_CLK_DIV is new Ada.Unchecked_Conversion - (Source => GP_Divider, - Target => CLK_DIV_Register); - - subtype CLK_SELECTED_Field is UInt32; - function CLK_SELECTED_Mask (SRC : CLK_CTRL_SRC_Field) - return CLK_SELECTED_Field; - - type CLK_Register is record - CTRL : CLK_CTRL_Register; - DIV : CLK_DIV_Register; - SELECTED : CLK_SELECTED_Field; - end record - with Size => (3 * 32), - Volatile; - - for CLK_Register use record - CTRL at 0 range 0 .. 31; - DIV at 0 range 32 .. 63; - SELECTED at 0 range 64 .. 95; - end record; - - type CLK_Array is array (Clock_Id range GPOUT0 .. RTC) of CLK_Register; - - type CLOCKS_Peripheral is record - CLK : aliased CLK_Array; - CLK_SYS_RESUS_CTRL : aliased CLK_SYS_RESUS_CTRL_Register; - CLK_SYS_RESUS_STATUS : aliased CLK_SYS_RESUS_STATUS_Register; - -- Reference clock frequency in kHz - FC0_REF_KHZ : aliased FC0_REF_KHZ_Register; - -- Minimum pass frequency in kHz. This is optional. Set to 0 if you are - -- not using the pass/fail flags - FC0_MIN_KHZ : aliased FC0_MIN_KHZ_Register; - -- Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if - -- you are not using the pass/fail flags - FC0_MAX_KHZ : aliased FC0_MAX_KHZ_Register; - -- Delays the start of frequency counting to allow the mux to settle\n - -- Delay is measured in multiples of the reference clock period - FC0_DELAY : aliased FC0_DELAY_Register; - -- The test interval is 0.98us * 2**interval, but let's call it 1us * - -- 2**interval\n The default gives a test interval of 250us - FC0_INTERVAL : aliased FC0_INTERVAL_Register; - -- Clock sent to frequency counter, set to 0 when not required\n Writing - -- to this register initiates the frequency count - FC0_SRC : aliased FC0_SRC_Register; - -- Frequency counter status - FC0_STATUS : aliased FC0_STATUS_Register; - -- Result of frequency measurement, only valid when status_done=1 - FC0_RESULT : aliased FC0_RESULT_Register; - -- enable clock in wake mode - WAKE_EN0 : aliased WAKE_EN0_Register; - -- enable clock in wake mode - WAKE_EN1 : aliased WAKE_EN1_Register; - -- enable clock in sleep mode - SLEEP_EN0 : aliased SLEEP_EN0_Register; - -- enable clock in sleep mode - SLEEP_EN1 : aliased SLEEP_EN1_Register; - -- indicates the state of the clock enable - ENABLED0 : aliased ENABLED0_Register; - -- indicates the state of the clock enable - ENABLED1 : aliased ENABLED1_Register; - -- Raw Interrupts - INTR : aliased INTR_Register; - -- Interrupt Enable - INTE : aliased INTE_Register; - -- Interrupt Force - INTF : aliased INTF_Register; - -- Interrupt status after masking & forcing - INTS : aliased INTS_Register; - end record - with Volatile; - - for CLOCKS_Peripheral use record - CLK at 16#00# range 0 .. 959; - CLK_SYS_RESUS_CTRL at 16#78# range 0 .. 31; - CLK_SYS_RESUS_STATUS at 16#7C# range 0 .. 31; - FC0_REF_KHZ at 16#80# range 0 .. 31; - FC0_MIN_KHZ at 16#84# range 0 .. 31; - FC0_MAX_KHZ at 16#88# range 0 .. 31; - FC0_DELAY at 16#8C# range 0 .. 31; - FC0_INTERVAL at 16#90# range 0 .. 31; - FC0_SRC at 16#94# range 0 .. 31; - FC0_STATUS at 16#98# range 0 .. 31; - FC0_RESULT at 16#9C# range 0 .. 31; - WAKE_EN0 at 16#A0# range 0 .. 31; - WAKE_EN1 at 16#A4# range 0 .. 31; - SLEEP_EN0 at 16#A8# range 0 .. 31; - SLEEP_EN1 at 16#AC# range 0 .. 31; - ENABLED0 at 16#B0# range 0 .. 31; - ENABLED1 at 16#B4# range 0 .. 31; - INTR at 16#B8# range 0 .. 31; - INTE at 16#BC# range 0 .. 31; - INTF at 16#C0# range 0 .. 31; - INTS at 16#C4# range 0 .. 31; - end record; - - CLOCKS_Periph : aliased CLOCKS_Peripheral - with Import, Address => RP2350_SVD.CLOCKS_Base; - - function CLK_SELECTED_Mask (SRC : CLK_CTRL_SRC_Field) - return CLK_SELECTED_Field - is (Shift_Left (1, Natural (SRC))); procedure Enable_XOSC is use RP2350_SVD.XOSC; @@ -250,35 +72,29 @@ package body RP.Clock is Configure_PLL (PLL_USB, PLL_48_MHz); -- Switch clk_sys to pll_sys - Set_SYS_Source (PLL_SYS); + CLOCKS_Periph.CLK_SYS_CTRL.AUXSRC := clksrc_pll_sys; + CLOCKS_Periph.CLK_SYS_DIV := (INT => 1, FRAC => 0); + CLOCKS_Periph.CLK_SYS_CTRL.SRC := clksrc_clk_sys_aux; -- Switch clk_usb to pll_usb - CLOCKS_Periph.CLK (USB).DIV.INT := 1; - CLOCKS_Periph.CLK (USB).CTRL.AUXSRC := PLL_SYS; -- the AUXSRC enum has the wrong name for some registers - while CLOCKS_Periph.CLK (USB).SELECTED /= CLK_SELECTED_Mask (USB_SRC_USB) loop - null; - end loop; + -- CLOCKS_Periph.CLK (USB).DIV.INT := 1; + -- CLOCKS_Periph.CLK (USB).CTRL.AUXSRC := PLL_SYS; -- the AUXSRC enum has the wrong name for some registers + -- while CLOCKS_Periph.CLK (USB).SELECTED /= CLK_SELECTED_Mask (USB_SRC_USB) loop + -- null; + -- end loop; -- Switch clk_adc to pll_usb - CLOCKS_Periph.CLK (ADC).DIV.INT := 1; - CLOCKS_Periph.CLK (ADC).CTRL.AUXSRC := PLL_SYS; - while CLOCKS_Periph.CLK (ADC).SELECTED /= CLK_SELECTED_Mask (ADC_SRC_USB) loop - null; - end loop; - - -- Switch clk_rtc to clk_xosc / 256 = 46_875 Hz - CLOCKS_Periph.CLK (RTC).DIV := - (INT => CLK_DIV_INT_Field (XOSC_Frequency / 46_875), - FRAC => 0); - CLOCKS_Periph.CLK (RTC).CTRL.AUXSRC := PLL_USB; - -- PLL_USB is actually XOSC here, CLK_RTC_CTRL_AUXSRC is different from the others. - -- clk_rtc SELECTED is hardwired, no point in polling it. + -- CLOCKS_Periph.CLK (ADC).DIV.INT := 1; + -- CLOCKS_Periph.CLK (ADC).CTRL.AUXSRC := PLL_SYS; + -- while CLOCKS_Periph.CLK (ADC).SELECTED /= CLK_SELECTED_Mask (ADC_SRC_USB) loop + -- null; + -- end loop; -- Switch clk_peri to pll_sys - CLOCKS_Periph.CLK (PERI).CTRL.AUXSRC := PLL_SYS; - while CLOCKS_Periph.CLK (PERI).SELECTED /= CLK_SELECTED_Mask (PERI_SRC_SYS) loop - null; - end loop; + -- CLOCKS_Periph.CLK (PERI).CTRL.AUXSRC := PLL_SYS; + -- while CLOCKS_Periph.CLK (PERI).SELECTED /= CLK_SELECTED_Mask (PERI_SRC_SYS) loop + -- null; + -- end loop; end Init_PLLs; procedure Initialize @@ -298,11 +114,15 @@ package body RP.Clock is if XOSC_Frequency > 0 then Reference := XOSC_Frequency; RP2350_SVD.XOSC.XOSC_Periph.STARTUP.DELAY_k := RP2350_SVD.XOSC.STARTUP_DELAY_Field (XOSC_Startup_Delay / 256); - Set_SYS_Source (XOSC); - Init_PLLs (XOSC_Frequency); + CLOCKS_Periph.CLK_SYS_CTRL.AUXSRC := xosc_clksrc; + CLOCKS_Periph.CLK_SYS_DIV := (INT => 1, FRAC => 0); + CLOCKS_Periph.CLK_SYS_CTRL.SRC := clksrc_clk_sys_aux; + -- Init_PLLs (XOSC_Frequency); else Reference := ROSC_Frequency; - Set_SYS_Source (ROSC); + CLOCKS_Periph.CLK_SYS_CTRL.AUXSRC := rosc_clksrc; + CLOCKS_Periph.CLK_SYS_DIV := (INT => 1, FRAC => 0); + CLOCKS_Periph.CLK_SYS_CTRL.SRC := clksrc_clk_sys_aux; Disable (PLL_SYS); Disable (PLL_USB); Disable (XOSC); @@ -315,16 +135,41 @@ package body RP.Clock is (CID : Clock_Id) is begin - CLOCKS_Periph.CLK (CID).CTRL.ENABLE := True; case CID is + when GPOUT0 => + CLOCKS_Periph.CLK_GPOUT0_CTRL.ENABLE := True; + when GPOUT1 => + CLOCKS_Periph.CLK_GPOUT1_CTRL.ENABLE := True; + when GPOUT2 => + CLOCKS_Periph.CLK_GPOUT2_CTRL.ENABLE := True; + when GPOUT3 => + CLOCKS_Periph.CLK_GPOUT3_CTRL.ENABLE := True; + when REF => + null; + when SYS => + null; + when PERI => + CLOCKS_Periph.CLK_PERI_CTRL.ENABLE := True; + when USB => + CLOCKS_Periph.CLK_USB_CTRL.ENABLE := True; + when ADC => + CLOCKS_Periph.CLK_ADC_CTRL.ENABLE := True; + when RTC => + raise Clock_Error with "RTC not supported on RP2350"; + when HSTX => + CLOCKS_Periph.CLK_HSTX_CTRL.ENABLE := True; + when PLL_SYS => + Configure_PLL (PLL_SYS, PLL_125_MHz); -- TODO correct default PLL setup + when GPIN0 => + null; + when GPIN1 => + null; + when PLL_USB => + Configure_PLL (PLL_USB, PLL_48_MHz); when ROSC => Enable_ROSC; when XOSC => Enable_XOSC; - when RTC => - raise Clock_Error with "RTC not supported on RP2350"; - when others => - null; end case; end Enable; @@ -332,65 +177,95 @@ package body RP.Clock is (CID : Clock_Id) is begin - if CID in CLOCKS_Periph.CLK'Range then - CLOCKS_Periph.CLK (CID).CTRL.ENABLE := False; - end if; - case CID is - when PLL_USB => - PLL_USB_Periph.PWR := (others => <>); + when GPOUT0 => + CLOCKS_Periph.CLK_GPOUT0_CTRL.ENABLE := False; + when GPOUT1 => + CLOCKS_Periph.CLK_GPOUT1_CTRL.ENABLE := False; + when GPOUT2 => + CLOCKS_Periph.CLK_GPOUT2_CTRL.ENABLE := False; + when GPOUT3 => + CLOCKS_Periph.CLK_GPOUT3_CTRL.ENABLE := False; + when REF => + raise Clock_Error with "Cannot disable REF clock"; + when SYS => + raise Clock_Error with "Cannot disable SYS clock"; + when PERI => + CLOCKS_Periph.CLK_PERI_CTRL.ENABLE := False; + when USB => + CLOCKS_Periph.CLK_USB_CTRL.ENABLE := False; + when ADC => + CLOCKS_Periph.CLK_ADC_CTRL.ENABLE := False; + when RTC => + raise Clock_Error with "RTC not supported on RP2350"; + when HSTX => + CLOCKS_Periph.CLK_HSTX_CTRL.ENABLE := True; when PLL_SYS => PLL_SYS_Periph.PWR := (others => <>); + when GPIN0 => + raise Clock_Error with "Cannot disable GPIN0 clock"; + when GPIN1 => + raise Clock_Error with "Cannot disable GPIN1 clock"; + when PLL_USB => + PLL_USB_Periph.PWR := (others => <>); when ROSC => RP2350_SVD.ROSC.ROSC_Periph.CTRL.ENABLE := RP2350_SVD.ROSC.DISABLE; when XOSC => RP2350_SVD.XOSC.XOSC_Periph.CTRL.ENABLE := RP2350_SVD.XOSC.DISABLE; - when RTC => - raise Clock_Error with "RTC not supported on RP2350"; - when others => - null; end case; end Disable; - procedure Set_Source - (GP : GP_Output; - Source : GP_Source) + function Enabled + (CID : Clock_Id) + return Boolean is - AUXSRC : CLK_CTRL_AUXSRC_Field - with Volatile, Address => CLOCKS_Periph.CLK (GP).CTRL.AUXSRC'Address; + use type RP2350_SVD.ROSC.CTRL_ENABLE_Field; + use type RP2350_SVD.XOSC.CTRL_ENABLE_Field; begin - case Source is + case CID is + when GPOUT0 => + return CLOCKS_Periph.CLK_GPOUT0_CTRL.ENABLE; + when GPOUT1 => + return CLOCKS_Periph.CLK_GPOUT1_CTRL.ENABLE; + when GPOUT2 => + return CLOCKS_Periph.CLK_GPOUT2_CTRL.ENABLE; + when GPOUT3 => + return CLOCKS_Periph.CLK_GPOUT3_CTRL.ENABLE; when REF => - AUXSRC := REF; + return True; when SYS => - AUXSRC := SYS; + return True; + when PERI => + return CLOCKS_Periph.CLK_PERI_CTRL.ENABLE; when USB => - AUXSRC := USB; + return CLOCKS_Periph.CLK_USB_CTRL.ENABLE; when ADC => - AUXSRC := ADC; - when HSTX => - AUXSRC := HSTX; + return CLOCKS_Periph.CLK_ADC_CTRL.ENABLE; when RTC => raise Clock_Error with "RTC not supported on RP2350"; + when HSTX => + return CLOCKS_Periph.CLK_HSTX_CTRL.ENABLE; when PLL_SYS => - AUXSRC := PLL_SYS; + return not PLL_SYS_Periph.PWR.PD; when GPIN0 => - AUXSRC := GPIN0; + return True; when GPIN1 => - AUXSRC := GPIN1; + return True; when PLL_USB => - AUXSRC := PLL_USB; + return not PLL_USB_Periph.PWR.PD; when ROSC => - AUXSRC := ROSC; + return RP2350_SVD.ROSC.ROSC_Periph.CTRL.ENABLE = RP2350_SVD.ROSC.ENABLE; when XOSC => - AUXSRC := XOSC; - when PERI => - -- PERI has no divider, so just copy it's AUXSRC - AUXSRC := CLOCKS_Periph.CLK (PERI).CTRL.AUXSRC; + return RP2350_SVD.XOSC.XOSC_Periph.CTRL.ENABLE = RP2350_SVD.XOSC.ENABLE; end case; + end Enabled; - -- Output clock with 50% duty cycle - CLOCKS_Periph.CLK (GP).CTRL.DC50 := True; + procedure Set_Source + (GP : GP_Output; + Source : GP_Source) + is + begin + raise Clock_Error with "Not implemented"; end Set_Source; procedure Set_Divider @@ -398,14 +273,9 @@ package body RP.Clock is Div : GP_Divider) is begin - CLOCKS_Periph.CLK (GP).DIV := To_CLK_DIV (Div); + raise Clock_Error with "Not implemented"; end Set_Divider; - function Enabled - (CID : Clock_Id) - return Boolean - is (CLOCKS_Periph.CLK (CID).CTRL.ENABLE); - function Frequency (CID : Countable_Clock_Id; Rounded : Boolean := True; @@ -445,46 +315,6 @@ package body RP.Clock is function ROSC_Frequency return Hertz - is (6_500_000); - - procedure Set_SYS_Source - (Source : SYS_Clock_Id) - is - SRC : CLK_CTRL_SRC_Field; - begin - case Source is - when PLL_SYS => - CLOCKS_Periph.CLK (SYS).CTRL.AUXSRC := PLL_SYS; - CLOCKS_Periph.CLK (SYS).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_AUX; - when GPIN0 => - CLOCKS_Periph.CLK (SYS).CTRL.AUXSRC := GPIN0; - CLOCKS_Periph.CLK (SYS).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_AUX; - when GPIN1 => - CLOCKS_Periph.CLK (SYS).CTRL.AUXSRC := GPIN1; - CLOCKS_Periph.CLK (SYS).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_AUX; - when PLL_USB => - CLOCKS_Periph.CLK (SYS).CTRL.AUXSRC := USB; - CLOCKS_Periph.CLK (SYS).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_AUX; - when ROSC => - Enable_ROSC; - CLOCKS_Periph.CLK (REF).CTRL.SRC := REF_SRC_ROSC; - CLOCKS_Periph.CLK (REF).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_REF; - when XOSC => - Enable_XOSC; - CLOCKS_Periph.CLK (REF).CTRL.SRC := REF_SRC_XOSC; - CLOCKS_Periph.CLK (REF).DIV := (INT => 1, FRAC => 0); - SRC := SYS_SRC_REF; - end case; - - CLOCKS_Periph.CLK (SYS).CTRL.SRC := SRC; - while CLOCKS_Periph.CLK (SYS).SELECTED /= CLK_SELECTED_Mask (SRC) loop - null; - end loop; - end Set_SYS_Source; + is (11_000_000); end RP.Clock; diff --git a/src/drivers/rp-clock.ads b/src/drivers/rp-clock.ads index 4347b3a..2b00843 100644 --- a/src/drivers/rp-clock.ads +++ b/src/drivers/rp-clock.ads @@ -57,9 +57,9 @@ is (CID : Clock_Id) return Boolean; - subtype SYS_Clock_Id is Clock_Id range PLL_SYS .. XOSC; - procedure Set_SYS_Source - (Source : SYS_Clock_Id); + -- subtype SYS_Clock_Id is Clock_Id range PLL_SYS .. XOSC; + -- procedure Set_SYS_Source + -- (Source : SYS_Clock_Id); subtype PLL_Clock_Id is Clock_Id with Static_Predicate => PLL_Clock_Id in PLL_SYS | PLL_USB; diff --git a/src/drivers/rp-i2c_master.adb b/src/drivers/rp-i2c_master.adb index 36ef65c..5104639 100644 --- a/src/drivers/rp-i2c_master.adb +++ b/src/drivers/rp-i2c_master.adb @@ -245,7 +245,8 @@ package body RP.I2C_Master is Stop : Boolean := True) is P : constant Any_I2C_Peripheral := Periph (This); - TX_EMPTY, STOP_DET : Boolean; + + STAT : INTR_Register; TX_ABRT_SOURCE : UInt32; Timeout, TX_Abort : Boolean := False; Read_Clear : CLR_Register with Volatile; @@ -261,8 +262,8 @@ package body RP.I2C_Master is DAT => Data (I), others => <>); loop - TX_EMPTY := P.RAW_INTR_STAT.TX_EMPTY; - exit when TX_EMPTY; + STAT := P.RAW_INTR_STAT; + exit when STAT.TX_EMPTY; Timeout := Time_Exceeded (This); TX_Abort := Timeout; exit when Timeout; @@ -279,8 +280,8 @@ package body RP.I2C_Master is loop Timeout := Time_Exceeded (This); TX_Abort := TX_Abort or else Timeout; - STOP_DET := P.RAW_INTR_STAT.STOP_DET; - exit when Timeout or else STOP_DET; + STAT := P.RAW_INTR_STAT; + exit when Timeout or else STAT.STOP_DET; end loop; if not Timeout then diff --git a/src/startup/rp2350/crt0.S b/src/startup/rp2350/crt0.S index 0d84cc4..2d6d120 100644 --- a/src/startup/rp2350/crt0.S +++ b/src/startup/rp2350/crt0.S @@ -511,9 +511,27 @@ bss_fill_test: platform_entry: - - - + // Enable coprocessors + ldr r0, =0xE000ED88 // CPACR + movs r1, #0x00F0 // CP10 | CP11 (FPU) + lsls r1, r1, #8 + orrs r1, #0xCC // CP5 | CP7 (DCP, RCP) + lsls r1, r1, #8 + orrs r1, #0x03 // CP0 (GPIOC) + str r1, [r0] + + // only initialize canary seeds if they haven't been (as to do so twice is a fault) + mrc p7, #1, apsr_nzcv, c0, c0, #0 + bmi 1f + // i dont think it much matters what we initialized to, as to have gotten here we must have not + // gone thru the bootrom (which a secure boot would have) + mcrr p7, #8, r0, r0, c0 + mcrr p7, #8, r0, r0, c1 + sev +1: + ldr r0, =__vectors + // Vector through our own table (SP, VTOR will not have been set up at + // this point). Same path for debugger entry and bootloader entry. movs r0, #0 msr msplim, r0 diff --git a/tests/alire.toml b/tests/alire.toml index caa1a21..39b2167 100644 --- a/tests/alire.toml +++ b/tests/alire.toml @@ -21,11 +21,11 @@ rp2040_hal = { path='..' } AUNIT_RUNTIME = "zfp-cross" AUNIT_BUILD_MODE = "Devel" -#[build-profiles] +[build-profiles] +"*" = "validation" #aunit = "release" -#"*" = "development" #usb_embedded = "release" -#atomic = "release" +atomic = "release" [configuration.values] rp2040_hal.Device = "rp2350"