System clocks configuration
This tutorial page explains the steps to configure an STM32 device core to run at a desired clock frequency. The necessary API is available by including the xpd_rcc_cc.h file of the respective package. The clock configuration consists of several individual API calls in order to provide means of error root cause detection for the user.
The STM32 devices all have a fixed frequency internal RC oscillator (High Speed Internal, HSI), and an external oscillator input with crystal driving capabilities (High Speed External, HSE). These sources can be selected as direct system clock sources, or they can be connected to the input of a PLL, which allows a much wider set of configurable frequencies.
Some devices have additional internal oscillators which can be configured in a similar manner as the general ones described below.
At device startup the device is always clocked directly from HSI. Therefore by default it does not need to be enabled like all other features. Nevertheless it can be enabled by the RCC_eHSI_Enable(); API call.
The XPD library requires precompile time information about the system clock sources for correct operation. Therefore the HSE API is only available when the HSE_VALUE_Hz is defined as the nominal frequency of the input clock in Hz. Two types of external clock sources can be handled by the STM32 devices:
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When a simple external clock is connected to the OSC_IN pin, the HSE has to be configured in Bypass mode:
RCC_eHSE_Config(OSC_BYPASS); -
When a crystal or ceramic resonator is connected to OSC_IN and OSC_OUT, the HSE crystal driver has to be enabled:
RCC_eHSE_Config(OSC_ON);
The Phase-Locked Loop of the STM32 devices can scale the input oscillator frequency to a desired value by its (STM32 line specific) multiplier and divider parameters. The State parameter shall be set to ENABLE, while the Source shall be set to HSI or HSE, and the configuration structure pointer shall be passed to the RCC_ePLL_Config() function to turn the PLL on.
The STM32 core is clocked by the HCLK, which is fed by the SYSCLK with a prescaler in between. The RCC_eHCLK_Config() API call handles together
- the SYSCLK input selection of the above sources,
- the HCLK input prescaler configuration,
- and the number of wait states (latency) for the embedded flash memory.
These settings are interdependent therefore have to be managed in one context. The flash latency is dependent on a number of system parameters, refer to the device's reference manual for details.
The peripheral bus clocks also need to be configured with a proper prescaler value, this can be done by the RCC_vPCLK1_Config() and RCC_vPCLK2_Config() API. Keep in mind that the ClockDividerType enumeration has a wider set of values than what can actually be configured. For HCLK prescaler CLK_DIV32 setting is prohibited, for PCLK prescalers all values above CLK_DIV16 are prohibited.
