Upload mtb-example-mcuboot-basic [3108]

Infineon · Dec 17, 2024 · 8e06bc9 · 8e06bc9
1 parent dbe1807
commit 8e06bc9
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diff --git a/README.md b/README.md
diff --git a/blinky_app/Makefile b/blinky_app/Makefile
@@ -41,8 +41,8 @@ APPNAME=blinky_app
 # If set to "true" or "1", display full command-lines when building.
 VERBOSE=
 
-# Disable the data cache for XMC7000 devices
-DEFINES+=CY_DISABLE_XMC7000_DATA_CACHE
+# Add additional defines to the build process (without a leading -D).
+DEFINES=
 
 ################################################################################
 # MCUboot Specific Configuration

diff --git a/bootloader_app/Makefile b/bootloader_app/Makefile
@@ -38,8 +38,8 @@ APPNAME=bootloader_app
 # If set to "true" or "1", display full command-lines when building.
 VERBOSE=
 
-# Disable the data cache for XMC7000 devices
-DEFINES+=CY_DISABLE_XMC7000_DATA_CACHE
+# Add additional defines to the build process (without a leading -D).
+DEFINES=
 
 ################################################################################
 # MCUboot Specific Configuration

diff --git a/templates/TARGET_KIT_XMC71_EVK_LITE_V1/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld b/templates/TARGET_KIT_XMC71_EVK_LITE_V1/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld
@@ -52,7 +52,8 @@ sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g.
 sram_used_by_boot                   = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
 
 cm0plus_sram_reserve                = CM0P_RAM_SIZE; /* cm0 sram size */
-cm7_sram_reserve                    = 0x00060000; /* 384K: cm7_1 sram size */
+cm7_sram_non_cache_reserve          = 0x00020000; /* 128K  : non-cacheable sram size */
+cm7_sram_reserve                    = 0x000A0000 - cm0plus_sram_reserve - cm7_sram_non_cache_reserve; /* 384K: cm7_1 sram size */
 
 code_flash_total_size               = 0x00410000; /* 4160K: total flash size */
 cm0plus_code_flash_reserve          = CM0P_FLASH_SIZE;
@@ -65,9 +66,12 @@ sram_base_address                   = 0x28000000;
 _base_SRAM_CM7_0                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_0                    = cm7_sram_reserve;
 /* In case of single CM7 device CM7_1 values should not be used */
-_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve + _size_SRAM_CM7_0;
+_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_1                    = cm7_sram_reserve;
 
+_base_SRAM_NON_CACHE                = _base_SRAM_CM7_1 + cm7_sram_reserve;
+_size_SRAM_NON_CACHE                = cm7_sram_non_cache_reserve;
+
 /* Code flash reservations */
 _base_CODE_FLASH_CM0P               = code_flash_base_address;
 _size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
@@ -129,6 +133,7 @@ MEMORY
     /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
     /* In our code example, User app will run on either CM7_0 core or CM7_1 core. So we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
     ram                 (rxw)       : ORIGIN = _base_SRAM_CM7_0,                  LENGTH = _size_SRAM_CM7_0                 /* SRAM */
+    ram_noncache        (rxw)       : ORIGIN = _base_SRAM_NON_CACHE,              LENGTH = _size_SRAM_NON_CACHE             /* Non-Cacheable SRAM */
     flash_cm0p          (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,             LENGTH = _size_CODE_FLASH_CM0P            /* CODE flash CM0+ */
     flash               (rx)        : ORIGIN = _base_CODE_FLASH_CM7_0,            LENGTH = _size_CODE_FLASH_CM7_0           /* CODE flash CM7_0/CM7_1 */
 
@@ -228,6 +233,11 @@ SECTIONS
         LONG (__data_start__)                               /* To   */
         LONG ((__data_end__ - __data_start__)/4)            /* Size */
 
+        /* Copy data section to noncache RAM */
+        LONG (__noncache_ramdata_lma_start__)               /* From */
+        LONG (__noncacheable_ram_start__)                   /* To   */
+        LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4)                 /* Size */
+
         /* Copy code to ITCM */
         LONG (__zero_table_end__)                           /* From */
         LONG (__itcm_start__)                                     /* To   */
@@ -315,13 +325,21 @@ SECTIONS
         KEEP(*(.cy_ramfunc*))
         . = ALIGN(32);
 
-        KEEP(*(cy_sharedmem*))
-        . = ALIGN(4);
-
         __data_end__ = .;
 
     } > ram AT>flash
 
+    __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+    .ram_noncache :
+    {
+        . = ALIGN(32);
+        __noncacheable_ram_start__ = .;
+        *(.cy_sharedmem)
+        . = ALIGN(4);
+        __noncacheable_ram_end__ = .;
+    } > ram_noncache AT>flash
+
 
     /* Place variables in the section that should not be initialized during the
     *  device startup.

diff --git a/templates/TARGET_KIT_XMC71_EVK_LITE_V1/xmc7xxx_partition.h b/templates/TARGET_KIT_XMC71_EVK_LITE_V1/xmc7xxx_partition.h
@@ -11,6 +11,7 @@
 #define SRAM_BASE_ADDRESS               CY_SRAM_BASE  /* SRAM START */
 #define TOTAL_RAM                       CY_SRAM_SIZE
 #define CM0PLUS_SRAM_RESERVE            0x00020000    /* 128K -> cm0plus */
+#define CM7_SRAM_NON_CACHE_RESERVE      0x00020000  /* 128K  :non-cacheable sram size */
 
 /* FLASH */
 #define CODE_FLASH_BASE_ADDRESS         CY_FLASH_LG_SBM_BASE                           /* FLASH START */
@@ -20,7 +21,7 @@
 /* In our code example, user app will run on either CM7_0 core or CM7_1 core.
  * So, we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
 /* CM7_1 RAM and FLASH */
-#define CM7_X_SRAM_RESERVE              (0x00080000 - CM0PLUS_SRAM_RESERVE)   /* 382KB -> cm7_x */
+#define CM7_X_SRAM_RESERVE              (0x000A0000 - CM0PLUS_SRAM_RESERVE - CM7_SRAM_NON_CACHE_RESERVE)   /* 384KB -> cm7_x */
 #define CM7_X_CODE_FLASH_RESERVE        0x00020000                            /* 128K CM7_x FLASH SIZE */
 
 /* SRAM reservations */
@@ -30,6 +31,9 @@
 #define SIZE_SRAM_CM7_0                 CM7_X_SRAM_RESERVE
 #define BASE_SRAM_CM7_1                 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
 
+#define BASE_SRAM_NON_CACHE             BASE_SRAM_CM7_1 + CM7_X_SRAM_RESERVE
+#define SIZE_SRAM_NON_CACHE             CM7_SRAM_NON_CACHE_RESERVE
+
 /* Code flash reservations */
 #define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
 #define SIZE_CODE_FLASH_CM0P            CM0PLUS_CODE_FLASH_RESERVE

diff --git a/templates/TARGET_KIT_XMC72_EVK/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld b/templates/TARGET_KIT_XMC72_EVK/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld
@@ -52,7 +52,8 @@ sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g.
 sram_used_by_boot                   = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
 
 cm0plus_sram_reserve                = CM0P_RAM_SIZE; /* cm0 sram size */
-cm7_sram_reserve                    = 0x00060000; /* 384K: cm7_1 sram size */
+cm7_sram_non_cache_reserve          = 0x00020000; /* 128K  : non-cacheable sram size */
+cm7_sram_reserve                    = 0x000A0000 - cm0plus_sram_reserve - cm7_sram_non_cache_reserve; /* 384K: cm7_1 sram size */
 
 code_flash_total_size               = 0x00830000; /* 8384K: total flash size */
 cm0plus_code_flash_reserve          = CM0P_FLASH_SIZE;
@@ -65,9 +66,12 @@ sram_base_address                   = 0x28000000;
 _base_SRAM_CM7_0                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_0                    = cm7_sram_reserve;
 /* In case of single CM7 device CM7_1 values should not be used */
-_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve + _size_SRAM_CM7_0;
+_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_1                    = cm7_sram_reserve;
 
+_base_SRAM_NON_CACHE                = _base_SRAM_CM7_1 + cm7_sram_reserve;
+_size_SRAM_NON_CACHE                = cm7_sram_non_cache_reserve;
+
 /* Code flash reservations */
 _base_CODE_FLASH_CM0P               = code_flash_base_address;
 _size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
@@ -129,6 +133,7 @@ MEMORY
     /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
     /* In our code example, User app will run on either CM7_0 core or CM7_1 core. So we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
     ram                 (rxw)       : ORIGIN = _base_SRAM_CM7_0,                  LENGTH = _size_SRAM_CM7_0                 /* SRAM */
+    ram_noncache        (rxw)       : ORIGIN = _base_SRAM_NON_CACHE,              LENGTH = _size_SRAM_NON_CACHE             /* Non-Cacheable SRAM */
     flash_cm0p          (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,             LENGTH = _size_CODE_FLASH_CM0P            /* CODE flash CM0+ */
     flash               (rx)        : ORIGIN = _base_CODE_FLASH_CM7_0,            LENGTH = _size_CODE_FLASH_CM7_0           /* CODE flash CM7_0/CM7_1 */
 
@@ -204,7 +209,6 @@ SECTIONS
         KEEP(*(.eh_frame*))
     } > flash
 
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -228,15 +232,20 @@ SECTIONS
         LONG (__data_start__)                               /* To   */
         LONG ((__data_end__ - __data_start__)/4)            /* Size */
 
+        /* Copy data section to noncache RAM */
+        LONG (__noncache_ramdata_lma_start__)               /* From */
+        LONG (__noncacheable_ram_start__)                   /* To   */
+        LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4)                 /* Size */
+
         /* Copy code to ITCM */
         LONG (__zero_table_end__)                           /* From */
-        LONG (__itcm_start__)                                     /* To   */
-        LONG ((__itcm_end__ - __itcm_start__)/4)  /* Size */
+        LONG (__itcm_start__)                               /* To   */
+        LONG ((__itcm_end__ - __itcm_start__)/4)            /* Size */
 
         /* Copy data to DTCM */
-        LONG (__itcm_flash_end__)                            /* From */
-        LONG (__dtcm_start__)                                      /* To   */
-        LONG ((__dtcm_end__ - __dtcm_start__)/4)   /* Size */
+        LONG (__itcm_flash_end__)                           /* From */
+        LONG (__dtcm_start__)                               /* To   */
+        LONG ((__dtcm_end__ - __dtcm_start__)/4)            /* Size */
 
         __copy_table_end__ = .;
     } > flash
@@ -248,9 +257,11 @@ SECTIONS
         __zero_table_start__ = .;
         LONG (__bss_start__)
         LONG ((__bss_end__ - __bss_start__)/4)
+
         __zero_table_end__ = .;
     } > flash
 
+
     /* itcm */
     .cy_itcm ORIGIN(itcm):
     {
@@ -315,13 +326,20 @@ SECTIONS
         KEEP(*(.cy_ramfunc*))
         . = ALIGN(32);
 
-        KEEP(*(cy_sharedmem*))
-        . = ALIGN(4);
-
         __data_end__ = .;
 
     } > ram AT>flash
 
+    __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+    .ram_noncache :
+    {
+        . = ALIGN(32);
+        __noncacheable_ram_start__ = .;
+        *(.cy_sharedmem)
+        . = ALIGN(4);
+        __noncacheable_ram_end__ = .;
+    } > ram_noncache AT>flash
 
     /* Place variables in the section that should not be initialized during the
     *  device startup.
@@ -435,7 +453,6 @@ SECTIONS
     {
         KEEP(*(.cy_efuse))
     } > efuse
-
 }
 
 

diff --git a/templates/TARGET_KIT_XMC72_EVK/xmc7xxx_partition.h b/templates/TARGET_KIT_XMC72_EVK/xmc7xxx_partition.h
@@ -11,6 +11,7 @@
 #define SRAM_BASE_ADDRESS               CY_SRAM_BASE  /* SRAM START */
 #define TOTAL_RAM                       CY_SRAM_SIZE
 #define CM0PLUS_SRAM_RESERVE            0x00020000    /* 128K -> cm0plus */
+#define CM7_SRAM_NON_CACHE_RESERVE      0x00020000  /* 128K  :non-cacheable sram size */
 
 /* FLASH */
 #define CODE_FLASH_BASE_ADDRESS         CY_FLASH_LG_SBM_BASE                           /* FLASH START */
@@ -20,7 +21,7 @@
 /* In our code example, user app will run on either CM7_0 core or CM7_1 core.
  * So, we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
 /* CM7_1 RAM and FLASH */
-#define CM7_X_SRAM_RESERVE              (0x00080000 - CM0PLUS_SRAM_RESERVE)   /* 382KB -> cm7_x */
+#define CM7_X_SRAM_RESERVE              (0x000A0000 - CM0PLUS_SRAM_RESERVE - CM7_SRAM_NON_CACHE_RESERVE)   /* 384KB -> cm7_x */
 #define CM7_X_CODE_FLASH_RESERVE        0x00020000                            /* 128K CM7_x FLASH SIZE */
 
 /* SRAM reservations */
@@ -30,6 +31,9 @@
 #define SIZE_SRAM_CM7_0                 CM7_X_SRAM_RESERVE
 #define BASE_SRAM_CM7_1                 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
 
+#define BASE_SRAM_NON_CACHE             BASE_SRAM_CM7_1 + CM7_X_SRAM_RESERVE
+#define SIZE_SRAM_NON_CACHE             CM7_SRAM_NON_CACHE_RESERVE
+
 /* Code flash reservations */
 #define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
 #define SIZE_CODE_FLASH_CM0P            CM0PLUS_CODE_FLASH_RESERVE

diff --git a/templates/TARGET_KIT_XMC72_EVK_MUR_43439M2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld b/templates/TARGET_KIT_XMC72_EVK_MUR_43439M2/COMPONENT_CM7/TOOLCHAIN_GCC_ARM/linker.ld
@@ -52,7 +52,8 @@ sram_private_for_srom               = 0x00000800; /* Private SRAM for SROM (e.g.
 sram_used_by_boot                   = 0x0; /* Used during boot by Cypress firmware (content will be overwritten on reset, so it should not be used for loadable sections in case of RAM build configurations) */
 
 cm0plus_sram_reserve                = CM0P_RAM_SIZE; /* cm0 sram size */
-cm7_sram_reserve                    = 0x00060000; /* 384K: cm7_1 sram size */
+cm7_sram_non_cache_reserve          = 0x00020000; /* 128K  : non-cacheable sram size */
+cm7_sram_reserve                    = 0x000A0000 - cm0plus_sram_reserve - cm7_sram_non_cache_reserve; /* 384K: cm7_1 sram size */
 
 code_flash_total_size               = 0x00830000; /* 8384K: total flash size */
 cm0plus_code_flash_reserve          = CM0P_FLASH_SIZE;
@@ -65,9 +66,12 @@ sram_base_address                   = 0x28000000;
 _base_SRAM_CM7_0                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_0                    = cm7_sram_reserve;
 /* In case of single CM7 device CM7_1 values should not be used */
-_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve + _size_SRAM_CM7_0;
+_base_SRAM_CM7_1                    = sram_base_address + cm0plus_sram_reserve;
 _size_SRAM_CM7_1                    = cm7_sram_reserve;
 
+_base_SRAM_NON_CACHE                = _base_SRAM_CM7_1 + cm7_sram_reserve;
+_size_SRAM_NON_CACHE                = cm7_sram_non_cache_reserve;
+
 /* Code flash reservations */
 _base_CODE_FLASH_CM0P               = code_flash_base_address;
 _size_CODE_FLASH_CM0P               = cm0plus_code_flash_reserve;
@@ -129,6 +133,7 @@ MEMORY
     /* The ram and flash regions control RAM and flash memory allocation for the CM7_0/CM7_1 core. */
     /* In our code example, User app will run on either CM7_0 core or CM7_1 core. So we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
     ram                 (rxw)       : ORIGIN = _base_SRAM_CM7_0,                  LENGTH = _size_SRAM_CM7_0                 /* SRAM */
+    ram_noncache        (rxw)       : ORIGIN = _base_SRAM_NON_CACHE,              LENGTH = _size_SRAM_NON_CACHE             /* Non-Cacheable SRAM */
     flash_cm0p          (rx)        : ORIGIN = _base_CODE_FLASH_CM0P,             LENGTH = _size_CODE_FLASH_CM0P            /* CODE flash CM0+ */
     flash               (rx)        : ORIGIN = _base_CODE_FLASH_CM7_0,            LENGTH = _size_CODE_FLASH_CM7_0           /* CODE flash CM7_0/CM7_1 */
 
@@ -204,7 +209,6 @@ SECTIONS
         KEEP(*(.eh_frame*))
     } > flash
 
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -228,15 +232,20 @@ SECTIONS
         LONG (__data_start__)                               /* To   */
         LONG ((__data_end__ - __data_start__)/4)            /* Size */
 
+        /* Copy data section to noncache RAM */
+        LONG (__noncache_ramdata_lma_start__)               /* From */
+        LONG (__noncacheable_ram_start__)                   /* To   */
+        LONG ((__noncacheable_ram_end__ - __noncacheable_ram_start__)/4)                 /* Size */
+
         /* Copy code to ITCM */
         LONG (__zero_table_end__)                           /* From */
-        LONG (__itcm_start__)                                     /* To   */
-        LONG ((__itcm_end__ - __itcm_start__)/4)  /* Size */
+        LONG (__itcm_start__)                               /* To   */
+        LONG ((__itcm_end__ - __itcm_start__)/4)            /* Size */
 
         /* Copy data to DTCM */
-        LONG (__itcm_flash_end__)                            /* From */
-        LONG (__dtcm_start__)                                      /* To   */
-        LONG ((__dtcm_end__ - __dtcm_start__)/4)   /* Size */
+        LONG (__itcm_flash_end__)                           /* From */
+        LONG (__dtcm_start__)                               /* To   */
+        LONG ((__dtcm_end__ - __dtcm_start__)/4)            /* Size */
 
         __copy_table_end__ = .;
     } > flash
@@ -248,9 +257,11 @@ SECTIONS
         __zero_table_start__ = .;
         LONG (__bss_start__)
         LONG ((__bss_end__ - __bss_start__)/4)
+
         __zero_table_end__ = .;
     } > flash
 
+
     /* itcm */
     .cy_itcm ORIGIN(itcm):
     {
@@ -315,13 +326,20 @@ SECTIONS
         KEEP(*(.cy_ramfunc*))
         . = ALIGN(32);
 
-        KEEP(*(cy_sharedmem*))
-        . = ALIGN(4);
-
         __data_end__ = .;
 
     } > ram AT>flash
 
+    __noncache_ramdata_lma_start__ = __etext + __data_end__ - __data_start__;
+
+    .ram_noncache :
+    {
+        . = ALIGN(32);
+        __noncacheable_ram_start__ = .;
+        *(.cy_sharedmem)
+        . = ALIGN(4);
+        __noncacheable_ram_end__ = .;
+    } > ram_noncache AT>flash
 
     /* Place variables in the section that should not be initialized during the
     *  device startup.
@@ -435,7 +453,6 @@ SECTIONS
     {
         KEEP(*(.cy_efuse))
     } > efuse
-
 }
 
 

diff --git a/templates/TARGET_KIT_XMC72_EVK_MUR_43439M2/xmc7xxx_partition.h b/templates/TARGET_KIT_XMC72_EVK_MUR_43439M2/xmc7xxx_partition.h
@@ -11,6 +11,7 @@
 #define SRAM_BASE_ADDRESS               CY_SRAM_BASE  /* SRAM START */
 #define TOTAL_RAM                       CY_SRAM_SIZE
 #define CM0PLUS_SRAM_RESERVE            0x00020000    /* 128K -> cm0plus */
+#define CM7_SRAM_NON_CACHE_RESERVE      0x00020000  /* 128K  :non-cacheable sram size */
 
 /* FLASH */
 #define CODE_FLASH_BASE_ADDRESS         CY_FLASH_LG_SBM_BASE                           /* FLASH START */
@@ -20,7 +21,7 @@
 /* In our code example, user app will run on either CM7_0 core or CM7_1 core.
  * So, we are giving the same FLASH/RAM base address and size for both the CM7_0/CM7_1 cores */
 /* CM7_1 RAM and FLASH */
-#define CM7_X_SRAM_RESERVE              (0x00080000 - CM0PLUS_SRAM_RESERVE)   /* 382KB -> cm7_x */
+#define CM7_X_SRAM_RESERVE              (0x000A0000 - CM0PLUS_SRAM_RESERVE - CM7_SRAM_NON_CACHE_RESERVE)   /* 384KB -> cm7_x */
 #define CM7_X_CODE_FLASH_RESERVE        0x00020000                            /* 128K CM7_x FLASH SIZE */
 
 /* SRAM reservations */
@@ -30,6 +31,9 @@
 #define SIZE_SRAM_CM7_0                 CM7_X_SRAM_RESERVE
 #define BASE_SRAM_CM7_1                 (SRAM_BASE_ADDRESS + CM0PLUS_SRAM_RESERVE)
 
+#define BASE_SRAM_NON_CACHE             BASE_SRAM_CM7_1 + CM7_X_SRAM_RESERVE
+#define SIZE_SRAM_NON_CACHE             CM7_SRAM_NON_CACHE_RESERVE
+
 /* Code flash reservations */
 #define BASE_CODE_FLASH_CM0P            CODE_FLASH_BASE_ADDRESS
 #define SIZE_CODE_FLASH_CM0P            CM0PLUS_CODE_FLASH_RESERVE