Verilog file for IO cells #84
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klayout might create a klayoutrc file in libs.tech/klayout. Ignore these type of files since they shouldn't get pushed. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Design definition are required to embed IO blocks directly into a design file. This file adds a basic representation of all digital and analog cells. Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
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Signed-off-by: Krzysztof Herman <141824113+KrzysztofHerman@users.noreply.github.com>
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This pull requests adds klayoutrc to the .gitignore file and also adds a verilog file to describe the current sg13g2_io cells.