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More LVS Updates #118

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May 21, 2024
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2 changes: 1 addition & 1 deletion .github/workflows/linting.yml
Original file line number Diff line number Diff line change
@@ -25,7 +25,7 @@ jobs:
lint_python:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Lint with flake8
6 changes: 3 additions & 3 deletions .github/workflows/lvs_regression.yml
Original file line number Diff line number Diff line change
@@ -34,7 +34,7 @@ jobs:
outputs:
lvs_table: ${{ steps.set-matrix.outputs.lvs_table }}
steps:
- uses: actions/checkout@v3
- uses: actions/checkout@v4
- id: set-matrix
run: |
cd ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/
@@ -67,7 +67,7 @@ jobs:
# Check that KLayout was successfully installed!
klayout -v

- uses: actions/checkout@v3
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Testing ${{ matrix.part }} for ${{ matrix.test }}
@@ -89,7 +89,7 @@ jobs:
# Check that KLayout was successfully installed!
klayout -v

- uses: actions/checkout@v3
- uses: actions/checkout@v4
with:
submodules: 'recursive'
- name: Testing LVS for SG13G2 cells
2 changes: 1 addition & 1 deletion ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md
Original file line number Diff line number Diff line change
@@ -222,4 +222,4 @@ Finally, after setting your option, you could execute the LVS using `Run Klayout

Upon executing the LVS, the result database will appear on your layout interface, allowing you to verify the outcome of the run similarly as shown above in Fig. 4.

Additionally, you can find the extracted netlist generated from your design at (`<layout_name>_extracted.cir`) in the same directory as the layout file.
Additionally, you can find the extracted netlist generated from your design at (`<layout_name>_extracted.cir`) in the same directory as the layout file.
Binary file modified ihp-sg13g2/libs.tech/klayout/tech/lvs/images/lvs_menus_2.png
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Original file line number Diff line number Diff line change
@@ -24,12 +24,12 @@
logger.info('Starting LVS CAP CONNECTIONS')

# === cap_mim ===
connect(cmim_btm, metal5_drw)
connect(cmim_btm, metal5_con)
connect(cmim_top, mim_via)
connect(mim_via, topmetal1_con)

# === rfcmim ===
connect(rfmim_btm, metal5_drw)
connect(rfmim_btm, metal5_con)
connect(rfmim_top, mim_via)
connect(rfmim_sub, ptap)

Original file line number Diff line number Diff line change
@@ -28,8 +28,8 @@ rfmimcap_exc = ind_drw.join(ind_pin)
# === MIMCAP ===
mimcap_exclude = pwell_block.join(rfmimcap_exc)

mim_top = mim_drw.overlapping(topmetal1_drw).and(metal5_drw)
mim_btm = metal5_drw.and(mim_drw).sized(0.6.um)
mim_top = mim_drw.overlapping(topmetal1_con).and(metal5_con)
mim_btm = metal5_con.and(mim_drw).sized(0.6.um)
mim_via = vmim_drw.join(topvia1_drw).and(mim_drw)
topvia1_n_cap = topvia1_drw.not(mim_via)

@@ -44,7 +44,7 @@ rfmim_top = mim_top.and(rfmim_area).not(rfmimcap_exc)
rfmim_btm = mim_btm.and(rfmim_area).covering(rfmim_top)
rfmim_dev = mim_drw.covering(rfmim_top).and(rfmim_btm)
rfmim_sub = ptap.extents.interacting(rfmim_area)
rfmeas_mk = metal5_drw.overlapping(rfmim_btm).and(rfmim_area)
rfmeas_mk = metal5_con.overlapping(rfmim_btm).and(rfmim_area)

# === svaricap ===
cap_exc = nsd_drw.join(trans_drw).join(emwind_drw)
Original file line number Diff line number Diff line change
@@ -171,6 +171,7 @@ class GeneralNTerminalExtractor < RBA::GenericDeviceExtractor
if bends.positive?
poly_sp_polygon = meas_mk.interacting(dev)
poly_sp = get_notch_min(poly_sp_polygon, 10 * length)
length = length + width
end

# Default values
Original file line number Diff line number Diff line change
@@ -48,7 +48,7 @@ schottky_mk = recog_diode.and(thickgateox_drw).not(diode_exclude)
.and(salblock_drw).and(nsd_block).and(nwell_holes)
.not(psd_drw).not(pwell).not(diode_exclude)

schottcky_p_ = cont_drw.and(activ_drw).and(metal1_drw)
schottcky_p_ = cont_drw.and(activ_drw).and(metal1_con)
.and(schottky_mk)

# schottky_nbl1 is a fixed device (0.3um X 1.0 um)
Original file line number Diff line number Diff line change
@@ -39,7 +39,7 @@ idiodevss_exc = esd_exc_d.join(nwell_drw.not_interacting(nwell_holes))
.join(pwell_block)
diodevss_exc = idiodevss_exc.join(nbulay_drw)

nw_diode = nwell_n_iso.not_interacting(pwell_block)
nw_diode = nwell_drw.not_interacting(pwell_block)
nw_idiode = nwell_iso.interacting(pwell_block)

#======================
Original file line number Diff line number Diff line change
@@ -24,7 +24,7 @@
logger.info('Starting GF180 LVS connectivity setup (Inter-layer)')

# Inter-layer
connect(pwell_deep, pwell)
connect(pwell_sub, pwell)
connect(pwell, ptap)
connect(nwell_drw, ntap)
connect(ntap, cont_drw)
@@ -34,26 +34,30 @@ connect(nsd_fet, cont_drw)
connect(psd_fet, cont_drw)
connect(cont_drw, metal1_con)
connect(metal1_con, via1_drw)
connect(via1_drw, metal2_drw)
connect(metal2_drw, via2_drw)
connect(via2_drw, metal3_drw)
connect(metal3_drw, via3_drw)
connect(via3_drw, metal4_drw)
connect(metal4_drw, via4_drw)
connect(via4_drw, metal5_drw)
connect(metal5_drw, topvia1_n_cap)
connect(via1_drw, metal2_con)
connect(metal2_con, via2_drw)
connect(via2_drw, metal3_con)
connect(metal3_con, via3_drw)
connect(via3_drw, metal4_con)
connect(metal4_con, via4_drw)
connect(via4_drw, metal5_con)
connect(metal5_con, topvia1_n_cap)
connect(topvia1_n_cap, topmetal1_con)
connect(topmetal1_con, topvia2_drw)
connect(topvia2_drw, topmetal2_con)

# salicide connection
connect(nsd_fet, nsd_ptap_abutt)
connect(nsd_ptap_abutt, ptap)
connect(psd_fet, psd_ntap_abutt)
connect(psd_ntap_abutt, ntap)

# Attaching labels
connect(activ_drw, activ_label)
connect(poly_con, gatpoly_label)
connect(metal1_con, metal1_text)
connect(metal2_drw, metal2_text)
connect(metal3_drw, metal3_text)
connect(metal4_drw, metal4_text)
connect(metal5_drw, metal5_text)
connect(metal2_con, metal2_text)
connect(metal3_con, metal3_text)
connect(metal4_con, metal4_text)
connect(metal5_con, metal5_text)
connect(topmetal1_con, topmetal1_text)
connect(topmetal2_con, topmetal2_text)

Original file line number Diff line number Diff line change
@@ -29,13 +29,16 @@ CHIP = extent.sized(0.0)
# === General Derivations ===
# nwell
nwell_iso = nwell_drw.and(nbulay_drw)
nwell_n_iso = nwell_drw.not(nbulay_drw)
nwell_holes = nwell_drw.holes.not(nwell_drw)

# pwell
pwell_pre = pwell_drw.join(CHIP.not(nwell_drw.join(pwell_block).join(digisub_drw)))
pwell_pre = CHIP.not(nwell_drw).not(pwell_block).not(digisub_drw)
digisub_pre = digisub_drw.sized(-1.nm).not(nwell_drw).not(pwell_block)
pwell = pwell_pre.join(digisub_pre)

# General pwell
pwell_sub = CHIP.not(digisub_drw).not(pwell_block).not(nbulay_drw.interacting(nwell_holes))

# psd, nsd active & res
psd = psd_drw
nsd_res = nsd_drw.and(psd).interacting(polyres_drw)
@@ -49,8 +52,12 @@ pactiv = activ_drw.and(psd)
res_mk = polyres_drw.join(res_drw)
poly_con = gatpoly_drw.not(res_mk)
metal1_con = metal1_drw.not(metal1_res)
topmetal1_con = topmetal1_drw.not(ind_drw)
topmetal2_con = topmetal2_drw.not(ind_drw)
metal2_con = metal2_drw.not(metal2_res)
metal3_con = metal3_drw.not(metal3_res)
metal4_con = metal4_drw.not(metal4_res)
metal5_con = metal5_drw.not(metal5_res)
topmetal1_con = topmetal1_drw.not(topmetal1_res).not(ind_drw)
topmetal2_con = topmetal2_drw.not(topmetal2_res).not(ind_drw)

# Gate FETs
tgate = gatpoly_drw.and(activ_drw).not(res_mk)
@@ -65,14 +72,28 @@ pgate_hv_base = pgate.and(thickgateox_drw)
nsd_fet = nactiv.not(nwell_drw).interacting(ngate).not(ngate).not_interacting(res_mk)
psd_fet = pactiv.and(nwell_drw).interacting(pgate).not(pgate).not_interacting(res_mk)

# n & p taps (short connections)
ntap = nactiv.and(nwell_n_iso).not(res_mk).not(recog_diode).not(gatpoly_drw)
ptap = pactiv.and(pwell).not(substrate_drw).not(res_mk).not(recog_diode).not(gatpoly_drw)

# Derived - Layers (Special)
nwell_holes = nwell_drw.holes.not(nwell_drw)
# n1/p1 taps labels
ntap1_lbl = text_drw.texts("well")
ntap1_mk = nwell_drw.interacting(ntap1_lbl)

ptap1_lbl = text_drw.texts("sub!")
ptap1_mk = substrate_drw.and(pwell).interacting(ptap1_lbl)

# n & p taps (short connections)
ntap = nactiv.and(nwell_drw).not(recog_diode).not(gatpoly_drw).not(ntap1_mk)
ptap = pactiv.and(pwell).not(ptap1_mk).not(recog_diode).not(gatpoly_drw)
ptap_holes = ptap.holes
ntap_holes = ntap.holes

# General pwell
pwell_deep = CHIP.not(digisub_drw).not(pwell_block).not(nbulay_drw.interacting(nwell_holes))
# S/D (salicide)
nsd_sal = nsd_fet.not(salblock_drw)
psd_sal = psd_fet.not(salblock_drw)

# n & p taps (salicide)
ntap_sal = ntap.not(salblock_drw)
ptap_sal = ptap.not(salblock_drw)

# n/p SD abutted with n/p taps (salicide)
nsd_ptap_abutt = nsd_sal.edges.and(ptap_sal.edges).extended(:in => 1.nm, :out => 1.nm)
psd_ntap_abutt = psd_sal.edges.and(ntap_sal.edges).extended(:in => 1.nm, :out => 1.nm)
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