diff --git a/.github/workflows/lvs_regression.yml b/.github/workflows/lvs_regression.yml
index ae5eb9c7..e5313079 100644
--- a/.github/workflows/lvs_regression.yml
+++ b/.github/workflows/lvs_regression.yml
@@ -58,9 +58,9 @@ jobs:
       - name: Installing Klayout
         run: |
           sudo apt update -qq -y
-          wget https://www.klayout.org/downloads/Ubuntu-22/klayout_0.28.14-1_amd64.deb
+          wget https://www.klayout.org/downloads/Ubuntu-22/klayout_0.29.0-1_amd64.deb
           # The dpkg command will fail complaining about missing dependencies.
-          sudo dpkg -i ./klayout_0.28.14-1_amd64.deb || true
+          sudo dpkg -i ./klayout_0.29.0-1_amd64.deb || true
           # The apt install command should install the missing dependencies
           # needed by KLayout above and finish the install.
           sudo apt install -f -y
@@ -73,3 +73,25 @@ jobs:
       - name: Testing ${{ matrix.part }} for ${{ matrix.test }}
         run: |
           make test-"$(python -c 'print("${{ matrix.part }}".upper())')"-${{ matrix.test }}
+
+  lvs_regression_cells:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Installing Klayout
+        run: |
+          sudo apt update -qq -y
+          wget https://www.klayout.org/downloads/Ubuntu-22/klayout_0.29.0-1_amd64.deb
+          # The dpkg command will fail complaining about missing dependencies.
+          sudo dpkg -i ./klayout_0.29.0-1_amd64.deb || true
+          # The apt install command should install the missing dependencies
+          # needed by KLayout above and finish the install.
+          sudo apt install -f -y
+          # Check that KLayout was successfully installed!
+          klayout -v
+
+      - uses: actions/checkout@v3
+        with:
+          submodules: 'recursive'
+      - name: Testing LVS for SG13G2 cells
+        run: |
+          make test-LVS-cells
diff --git a/.gitignore b/.gitignore
index ad605536..e8c01c08 100644
--- a/.gitignore
+++ b/.gitignore
@@ -173,3 +173,4 @@ cython_debug/
 unit_tests_*
 lvs_run_*
 *_extracted.cir
+cells_tests_*
\ No newline at end of file
diff --git a/Makefile b/Makefile
index 6cdef419..24806360 100644
--- a/Makefile
+++ b/Makefile
@@ -60,6 +60,14 @@ test-LVS-% : env
 	@. $(VENV_RUN_COMMAND); echo "Running Klayout-LVS regression for $* device"
 	@. $(VENV_RUN_COMMAND); cd $(KLAYOUT_LVS_TESTS) && make test-LVS-$*
 
+#=================================
+# -------- test-LVS-cells --------
+#=================================
+
+test-LVS-cells: env
+	@. $(VENV_RUN_COMMAND); echo "Running Klayout-LVS for SG13G2 cells"
+	@. $(VENV_RUN_COMMAND); cd $(KLAYOUT_LVS_TESTS) && make test-LVS-cells
+
 #=================================
 # -------- test-LVS-switch -------
 #=================================
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md b/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md
index 3bd4347a..b23de49b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/README.md
@@ -19,21 +19,23 @@ Explains how to use the SG13G2 LVS rule decks.
 
 ```text
 📁 lvs
- ┣ 📁testing               Testing environment directory for SG13G2 LVS. 
- ┣ 📁rule_decks            Holds all LVS rule decks used for SG13G2.
- ┣ sg13g2.lvs              Main LVS runset that call all rule decks.
- ┣ 📜README.md             This file to document LVS for SG13G2.
- ┗ 📜run_lvs.py            Main python script used for SG13G2 LVS.
+ ┣ 📁testing               Directory for the SG13G2 LVS testing environment.
+ ┣ 📁rule_decks            Contains all LVS rule decks used for SG13G2.
+ ┣ 📜sg13g2.lvs            Main LVS runset that calls all rule decks.
+ ┣ 📜README.md             Documentation for SG13G2 LVS.
+ ┗ 📜run_lvs.py            Main Python script for SG13G2 LVS run.
  ```
 
 ## Prerequisites
 
 You need the following set of tools installed to be able to run SG13G2 LVS:
 
-At a minimum:
-
 - Python 3.9+
-- KLayout 0.28.14+
+- KLayout 0.29.0+
+
+We have tested this using the following setup:
+- Python 3.9.18
+- KLayout 0.29.0
 
 ## Installation
 
@@ -43,59 +45,6 @@ To install the required Python packages, execute the following command:
 pip install -r ../../../../../requirements.txt
 ```
 
-## Devices Status
-
-The following table explains the list of available SG13G2 devices we have supported in our LVS runset.
-
-| Device          | Tested           |
-|-----------------|------------------|
-| **MOSFET**      |                  |
-| sg13_lv_nmos    |:white_check_mark:|
-| sg13_hv_nmos    |:white_check_mark:|
-| sg13_lv_pmos    |:white_check_mark:|
-| sg13_hv_pmos    |:white_check_mark:|
-| **RF-MOSFET**   |                  |
-| rfnmos          |:white_check_mark:|
-| rfnmosHV        |:white_check_mark:|
-| rfpmos          |:white_check_mark:|
-| rfpmosHV        |:white_check_mark:|
-| **BJTs**        |                  |
-| npn13G2         |:white_check_mark:|
-| npn13G2L        |:white_check_mark:|
-| npn13G2V        |:white_check_mark:|
-| pnpMPA          |:white_check_mark:|
-| **Diodes**      |                  |
-| dantenna        |:white_check_mark:|
-| dpantenna       |:white_check_mark:|
-| schottky_nbl1   |:white_check_mark:|
-| **Resistors**   |                  |
-| rsil            |:white_check_mark:|
-| rppd            |:white_check_mark:|
-| rhigh           |:white_check_mark:|
-| lvsres          |:white_check_mark:|
-| **Capacitors**  |                  |
-| SVaricap        |:white_check_mark:|
-| cap_cmim        |:white_check_mark:|
-| rfcmim          |:white_check_mark:|
-| **ESD**         |                  |
-| diodevdd_4kv    |:white_check_mark:|
-| diodevdd_2kv    |:white_check_mark:|
-| diodevss_4kv    |:white_check_mark:|
-| diodevss_2kv    |:white_check_mark:|
-| idiodevdd_4kv   |:white_check_mark:|
-| idiodevdd_2kv   |:white_check_mark:|
-| idiodevss_4kv   |:white_check_mark:|
-| idiodevss_2kv   |:white_check_mark:|
-| nmoscl_2        |:white_check_mark:|
-| nmoscl_4        |:white_check_mark:|
-| **Inductors**   |                  |
-| inductor        |:white_check_mark:|
-| inductor3       |:white_check_mark:|
-| **Taps**        |                  |
-| ptap1           |:white_check_mark:|
-| ntap1           |:white_check_mark:|
-
-
 ## Usage
 
 You have the option to execute the SG13G2-LVS through either a Python script via the command-line interface [CLI](#cli) or by the Klayout graphical user interface [GUI](#gui), as detailed in the subsequent usage sections.
@@ -115,7 +64,7 @@ The `run_lvs.py` script takes your gds and netlist files to run LVS rule decks w
 
 **Options:**
 
-- `--help -h `                        Displays this help message.
+- `--help -h`                         Displays this help message.
 
 - `--layout=<layout_path>`            Specifies the file path of the input GDS file.
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs
index 4b571a94..cd812c02 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_devices.lvs
@@ -111,11 +111,11 @@ class DeviceCustomInd < RBA::DeviceClassInductor
     add_terminals(name, num, 1)
 
     # 5% tolerance for w,s,d:
-    equal_device_parameters = RBA::EqualDeviceParameters::new(parameter_id('w'), 0.0, 0.05)
-    equal_device_parameters += RBA::EqualDeviceParameters::new(parameter_id('s'), 0.0, 0.05)
-    equal_device_parameters += RBA::EqualDeviceParameters::new(parameter_id('d'), 0.0, 0.05)
+    equal_ind_parameters = RBA::EqualDeviceParameters::new(parameter_id('w'), 0.0, 0.05)
+    equal_ind_parameters += RBA::EqualDeviceParameters::new(parameter_id('s'), 0.0, 0.05)
+    equal_ind_parameters += RBA::EqualDeviceParameters::new(parameter_id('d'), 0.0, 0.05)
     # applies the compare delegate:
-    self.equal_parameters = equal_device_parameters
+    self.equal_parameters = equal_ind_parameters
 
     self.combiner = nil
     self.supports_serial_combination=false
@@ -147,20 +147,17 @@ class RES2 < RBA::DeviceClassResistor
   end
 end
 
-# MIMCAP device class
-class MIMCap < RBA::DeviceClassCapacitor
-  def initialize
-    super
-    enable_parameter('C', false)
-    enable_parameter('A', true)
-    enable_parameter('P', true)
-  end
-end
-
 # Diode device class
 class EnDiode < RBA::DeviceClassDiode
   def initialize
-    super
+    
+    # 1% tolerance for A,P:
+    equal_diode_parameters = RBA::EqualDeviceParameters::new(parameter_id('A'), 0.0, 0.01)
+    equal_diode_parameters += RBA::EqualDeviceParameters::new(parameter_id('P'), 0.0, 0.01)
+    # applies the compare delegate:
+    self.equal_parameters = equal_diode_parameters
+
+    # combiner
     self.combiner = DiodeDeviceCombiner.new
     self.supports_serial_combination=true
     self.supports_parallel_combination=true
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_mim_extractor.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_mim_extractor.lvs
index 968203ec..60d39712 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_mim_extractor.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_mim_extractor.lvs
@@ -33,9 +33,11 @@ class DeviceCustomMIM < RBA::DeviceClassCapacitor
     clear_equivalent_terminal_ids
 
     # Adding params
-    add_parameter(RBA::DeviceParameterDefinition.new('w', 'width', 0, true, 1e-6))
-    add_parameter(RBA::DeviceParameterDefinition.new('l', 'length', 0, true, 1e-6))
-    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true, 1.0))
+    add_parameter(RBA::DeviceParameterDefinition.new('w', 'width', 0, false))
+    add_parameter(RBA::DeviceParameterDefinition.new('l', 'length', 0, false))
+    add_parameter(RBA::DeviceParameterDefinition.new('A', 'area', 0, true))
+    add_parameter(RBA::DeviceParameterDefinition.new('P', 'perimeter', 0, true))
+    add_parameter(RBA::DeviceParameterDefinition.new('m', 'multiplier', 1, true))
 
     # Adding terminals
     ter1 = add_terminal(RBA::DeviceTerminalDefinition.new("mim_top"))
@@ -46,7 +48,7 @@ class DeviceCustomMIM < RBA::DeviceClassCapacitor
     # Adding extra param & terminal for rfcmim
     return unless name.downcase.include?('rfcmim')
 
-    add_parameter(RBA::DeviceParameterDefinition.new('wfeed', 'feed width', 0, true, 1e-6))
+    add_parameter(RBA::DeviceParameterDefinition.new('wfeed', 'feed width', 0, true))
     sub_ter = add_terminal(RBA::DeviceTerminalDefinition.new("mim_sub"))
     sub_ter.name = "mim_sub"
   end
@@ -170,6 +172,8 @@ class MIMCAPExtractor < RBA::GenericDeviceExtractor
       device.set_parameter('w', width * $unit)
       device.set_parameter('l', length * $unit)
     end
+    device.set_parameter('A', width * length * $unit * $unit)
+    device.set_parameter('P', (width + length) * 2 * $unit)
 
   end
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_reader.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_reader.lvs
index aca009a1..bf60097e 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_reader.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/custom_reader.lvs
@@ -21,8 +21,37 @@
 
 # Custom reader for subcircuit models
 class CustomReader < RBA::NetlistSpiceReaderDelegate
+  # Cleanup sch for R, C elements
+  def clean_sch(line, element)
+    line = line.delete('[]$\\/')
+
+    # Extracting parameters with values
+    valid_params = line.scan(/\b\w+\s*=\s*\S+\b/)
+
+    case element
+    when 'R'
+      # For 2 term res [<nets> <model> <params>]
+      num_terms = 3
+    when 'C'
+      # Determine number of terms based on component type
+      num_terms =
+        if line.downcase.include?('varicap')
+          5
+        elsif line.downcase.include?('rfcmim')
+          4
+        else
+          3
+        end
+    end
+    line_no_param = line.split(' ').take(num_terms).join(' ')
+    "#{line_no_param.strip} #{valid_params.join(' ')}"
+  end
+
   # Override parse_element method to handle exceptions gracefully
   def parse_element(line, element)
+    # Prep sch for R, C
+    line = clean_sch(line, element) if %w[R C].include?(element)
+
     super
   rescue StandardError
     case element
@@ -265,13 +294,11 @@ class CustomReader < RBA::NetlistSpiceReaderDelegate
 
   # Map parameters for a diode device.
   def map_diode_params(device, model, params)
-    if model.downcase.include?('diodev') || model.downcase.include?('schottky') || model.downcase.include?('nmoscl')
-      device.set_parameter('m', params['M'] || 1.0)
-    else
+    unless model.downcase.include?('diodev') || model.downcase.include?('schottky') || model.downcase.include?('nmoscl')
       device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
       device.set_parameter('P', (params['P'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
-      device.set_parameter('m', params['M'] || 1.0)
     end
+    device.set_parameter('m', params['M'] || 1.0)
   end
 
   # Map parameters for a capacitor device.
@@ -279,6 +306,11 @@ class CustomReader < RBA::NetlistSpiceReaderDelegate
     device.set_parameter('w', (params['W'] || 0.0) * 1e6)
     device.set_parameter('l', (params['L'] || 0.0) * 1e6)
     device.set_parameter('m', params['M'] || params['MF'] || 1.0) if model.downcase.include?('cap_cmim')
+
+    if model.downcase.include?('mim')
+      device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
+      device.set_parameter('P', (params['P'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+    end
     return unless model.downcase.include?('rfcmim')
 
     device.set_parameter('wfeed', (params['WFEED'] || 0.0) * 1e6)
@@ -288,7 +320,8 @@ class CustomReader < RBA::NetlistSpiceReaderDelegate
   def map_resistor_params(device, model, params)
     if model.downcase.include?('tap')
       device.set_parameter('A', (params['A'] || ((params['W'] || 0.0) * (params['L'] || 0.0))) * 1e12)
-      device.set_parameter('P', (params['P'] || params['PERIM'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
+      device.set_parameter('P',
+                           (params['P'] || params['PERIM'] || (((params['W'] || 0.0) + (params['L'] || 0.0)) * 2)) * 1e6)
     elsif RES_DEV.any? { |res| model.downcase.start_with?(res) }
       device.set_parameter('w', (params['W'] || 0.0) * 1e6)
       device.set_parameter('l', (params['L'] || 0.0) * 1e6)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs
index 6006f701..2d79ab04 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/diode_derivations.lvs
@@ -29,7 +29,7 @@ diode_exclude = gatpoly_drw.join(nsd_drw)
                 .join(activ_mask).join(recog_esd).join(ind_drw)
                 .join(ind_pin).join(substrate_drw)
 
-antenna_d_exc = pwell_block.join(nbulay_drw).join(salblock_drw)
+antenna_d_exc = pwell_block.join(salblock_drw)
                 .join(nsd_block).join(diode_exclude)
 
 antenna_d_mk = recog_diode.not(antenna_d_exc)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
index a5356de5..5d2d5013 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs
@@ -49,12 +49,12 @@ connect(topvia2_drw, topmetal2_con)
 # Attaching labels
 connect(activ_drw, activ_label)
 connect(poly_con, gatpoly_label)
-connect(metal1_con, metal1_label)
-connect(metal2_drw, metal2_label)
-connect(metal3_drw, metal3_label)
-connect(metal4_drw, metal4_label)
-connect(metal5_drw, metal5_label)
-connect(topmetal1_con, topmetal1_label)
-connect(topmetal2_con, topmetal2_label)
+connect(metal1_con, metal1_text)
+connect(metal2_drw, metal2_text)
+connect(metal3_drw, metal3_text)
+connect(metal4_drw, metal4_text)
+connect(metal5_drw, metal5_text)
+connect(topmetal1_con, topmetal1_text)
+connect(topmetal2_con, topmetal2_text)
 
 logger.info('Starting SG13G2 LVS connectivity setup (Global)')
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs
index 5bed6542..d3eef551 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_derivations.lvs
@@ -33,7 +33,7 @@ nwell_n_iso = nwell_drw.not(nbulay_drw)
 
 # pwell
 pwell_pre = pwell_drw.join(CHIP.not(nwell_drw.join(pwell_block).join(digisub_drw)))
-digisub_pre = digisub_drw.sized(-1.nm)
+digisub_pre = digisub_drw.sized(-1.nm).not(nwell_drw).not(pwell_block)
 pwell = pwell_pre.join(digisub_pre)
 
 # psd, nsd active & res
@@ -70,7 +70,7 @@ ntap = nactiv.and(nwell_n_iso).not(res_mk).not(recog_diode).not(gatpoly_drw)
 ptap = pactiv.and(pwell).not(substrate_drw).not(res_mk).not(recog_diode).not(gatpoly_drw)
 
 # Derived - Layers (Special)
-nwell_holes = nwell_drw.holes
+nwell_holes = nwell_drw.holes.not(nwell_drw)
 ptap_holes = ptap.holes
 ntap_holes = ntap.holes
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs
index fbf0b2eb..3dbbd68f 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_connections.lvs
@@ -27,10 +27,9 @@ logger.info('Starting Inductor CONNECTIONS')
 connect(ind2_ports, ind_pin)
 connect(ind_pin, ind_text)
 connect(ind_pin, topmetal2_con)
-connect(ind2_sub, pwell_block)
-connect(pwell_block, pwell)
+connect(ind2_sub, pwell)
 
 # ind3
 connect(ind3_ports, ind_pin)
 connect(ind_pin, topmetal1_con)
-connect(ind3_sub, pwell_block)
+connect(ind3_sub, pwell)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_derivations.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_derivations.lvs
index 2375a66b..ed738b32 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_derivations.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_derivations.lvs
@@ -43,10 +43,10 @@ ind_port_lc = ind_ports_.interacting(ind_text.texts("LC"))
 ind2_ports = ind_port_la.join(ind_port_lb)
 ind2_core = ind_core_.interacting(ind_port_la, 1).interacting(ind_port_lb, 1)
 ind2_mk = ind_drw.interacting(ind2_core).interacting(ind2_ports).not_interacting(ind_port_lc)
-ind2_sub = pwell_block.and(ind_drw).interacting(ind2_core)
+ind2_sub = pwell_block.and(ind_drw).interacting(ind2_core).sized(1.nm)
 
 # inductor3
 ind3_ports = ind_port_la.join(ind_port_lb).join(ind_port_lc)
 ind3_core = ind_core_.interacting(ind_port_la, 1).interacting(ind_port_lb, 1).interacting(ind_port_lc, 1)
 ind3_mk = ind_drw.interacting(ind3_core).interacting(ind3_ports)
-ind3_sub = pwell_block.and(ind_drw).interacting(ind3_core)
+ind3_sub = pwell_block.and(ind_drw).interacting(ind3_core).sized(1.nm)
\ No newline at end of file
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_extraction.lvs b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_extraction.lvs
index 8c565ee2..7272b32b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_extraction.lvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/ind_extraction.lvs
@@ -32,9 +32,6 @@ extract_devices(GeneralNTerminalExtractor.new('inductor', 2), {
                   'dev_mk' => ind2_mk,
                   'sub_mk' => ind2_sub
                 })
-tolerance('inductor', 'w', 0, 0.1)
-tolerance('inductor', 's', 0, 0.1)
-tolerance('inductor', 'd', 0, 0.1)
 
 # ind3
 logger.info('Extracting Inductor3 device')
@@ -45,6 +42,3 @@ extract_devices(GeneralNTerminalExtractor.new('inductor3', 3), {
                   'dev_mk' => ind3_mk,
                   'sub_mk' => ind3_sub
                 })
-tolerance('inductor3', 'w', 0, 0.1)
-tolerance('inductor3', 's', 0, 0.1)
-tolerance('inductor3', 'd', 0, 0.1)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py
index 46e03447..16c289e4 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/run_lvs.py
@@ -72,14 +72,12 @@ def check_klayout_version():
         logging.error("Was not able to get klayout version properly.")
         exit(1)
     elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
-        if klayout_v_list[1] < 28 or (
-            klayout_v_list[1] == 28 and klayout_v_list[2] <= 13
-        ):
-            logging.error("Prerequisites at a minimum: KLayout 0.28.14")
+        if klayout_v_list[1] < 29:
+            logging.error("Prerequisites at a minimum: KLayout 0.29.0")
             logging.error(
                 "Using this klayout version has not been assessed. Limits are unknown"
             )
-            # exit(1)
+            exit(1)
 
     logging.info(f"Your Klayout version is: {klayout_v_}")
 
@@ -191,12 +189,13 @@ def generate_klayout_switches(arguments, layout_path, netlist_path):
     switches = dict()
 
     if arguments["--run_mode"] in ["flat", "deep"]:
-        switches["run_mode"] = arguments["--run_mode"]
+        run_mode = arguments["--run_mode"]
     else:
         logging.error("Allowed klayout modes are (flat , deep) only")
-        exit()
+        exit(1)
 
     switches = {
+        "run_mode": run_mode,
         "no_net_names": "true" if arguments.get("--no_net_names") else "false",
         "spice_comments": "true" if arguments.get("--spice_comments") else "false",
         "net_only": "true" if arguments.get("--net_only") else "false",
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
index dad87c29..2809a23c 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/Makefile
@@ -39,6 +39,15 @@ test-LVS-%:
 	@echo "========== LVS-$* testing =========="
 	@ python3 run_regression.py --device=$*
 
+#================================
+# ------ test-LVS-stdcells ------
+#================================
+
+.ONESHELL:
+test-LVS-cells:
+	@echo "========== SG13G2-Cells Testing =========="
+	@ python3 run_regression_cells.py
+
 #=================================
 # -------- test-LVS-switch -------
 #=================================
@@ -49,6 +58,10 @@ test-LVS-switch:
 	@python3 ../run_lvs.py --layout=testcases/extraction_checking/sg13_lv_nmos.gds --netlist=testcases/extraction_checking/sg13_lv_nmos.cdl --run_mode=deep --run_dir=test_nmos_deep
 	@python3 ../run_lvs.py --layout=testcases/extraction_checking/sg13_lv_nmos.gds --netlist=testcases/extraction_checking/sg13_lv_nmos.cdl --run_mode=flat --run_dir=test_nmos_flat
 
+#==============================
+# -------- LIST DEVICES -------
+#==============================
+
 .ONESHELL:
 list-devices:
 	@echo "test-LVS-MOS"
@@ -71,6 +84,7 @@ help:
 	@echo "... all                        (the default if no target is provided             )"
 	@echo "... test-LVS                   (To run LVS for all devices with switching test   )"
 	@echo "... test-LVS-main              (To run LVS for all devices                       )"
+	@echo "... test-LVS-stdcells          (To run LVS for all standard cells                )"
 	@echo "... test-LVS-switch            (To run simple LVS switching test                 )"
 	@echo "... test-LVS-<device>          (To run LVS for specific device group             )"
 	@echo "... list-devices               (To list all available device groups              )"
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/README.md b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/README.md
index 0168e9c7..699b4884 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/README.md
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/README.md
@@ -6,10 +6,11 @@ Explains how to test SG13G2 LVS rule decks.
 
 ```text
 📁 testing
- ┣ 📜README.md              This file to document the testing directory.
- ┣ 📜Makefile               Used for SG13G2 LVS rule deck testing.
- ┣ 📜run_regression.py      Main regression script used for LVS testing.
- ┣ 📁testcases              All testcases used for LVS testing.
+ ┣ 📜README.md                 This file documents the contents of the testing directory.
+ ┣ 📜Makefile                  Used for testing the SG13G2 LVS rule deck.
+ ┣ 📜run_regression.py         Main regression script for testing SG13G2 devices.
+ ┣ 📜run_regression_cells.py   Main regression script for testing SG13G2 cells.
+ ┣ 📁testcases                 Contains all test cases used for LVS testing.
  ```
 
 ## Prerequisites
@@ -18,11 +19,11 @@ At a minimum:
 
 You need the following set of tools installed to be able to run the regression:
 - Python 3.9+
-- KLayout 0.28.14+
+- KLayout 0.29.0+
 
 We have tested this using the following setup:
 - Python 3.9.18
-- KLayout 0.28.16
+- KLayout 0.29.0
 
 ## Installation
 
@@ -32,20 +33,72 @@ To install the required Python packages, execute the following command:
 pip install -r ../../../../../../requirements.txt
 ```
 
-## Usage
+## Devices Status
+
+The following table explains the list of available SG13G2 devices we have supported in our LVS runset.
+
+| Device          | Tested           |
+|-----------------|------------------|
+| **MOSFET**      |                  |
+| sg13_lv_nmos    |:white_check_mark:|
+| sg13_hv_nmos    |:white_check_mark:|
+| sg13_lv_pmos    |:white_check_mark:|
+| sg13_hv_pmos    |:white_check_mark:|
+| **RF-MOSFET**   |                  |
+| rfnmos          |:white_check_mark:|
+| rfnmosHV        |:white_check_mark:|
+| rfpmos          |:white_check_mark:|
+| rfpmosHV        |:white_check_mark:|
+| **BJTs**        |                  |
+| npn13G2         |:white_check_mark:|
+| npn13G2L        |:white_check_mark:|
+| npn13G2V        |:white_check_mark:|
+| pnpMPA          |:white_check_mark:|
+| **Diodes**      |                  |
+| dantenna        |:white_check_mark:|
+| dpantenna       |:white_check_mark:|
+| schottky_nbl1   |:white_check_mark:|
+| **Resistors**   |                  |
+| rsil            |:white_check_mark:|
+| rppd            |:white_check_mark:|
+| rhigh           |:white_check_mark:|
+| lvsres          |:white_check_mark:|
+| **Capacitors**  |                  |
+| SVaricap        |:white_check_mark:|
+| cap_cmim        |:white_check_mark:|
+| rfcmim          |:white_check_mark:|
+| **ESD**         |                  |
+| diodevdd_4kv    |:white_check_mark:|
+| diodevdd_2kv    |:white_check_mark:|
+| diodevss_4kv    |:white_check_mark:|
+| diodevss_2kv    |:white_check_mark:|
+| idiodevdd_4kv   |:white_check_mark:|
+| idiodevdd_2kv   |:white_check_mark:|
+| idiodevss_4kv   |:white_check_mark:|
+| idiodevss_2kv   |:white_check_mark:|
+| nmoscl_2        |:white_check_mark:|
+| nmoscl_4        |:white_check_mark:|
+| **Inductors**   |                  |
+| inductor        |:white_check_mark:|
+| inductor3       |:white_check_mark:|
+| **Taps**        |                  |
+| ptap1           |:white_check_mark:|
+| ntap1           |:white_check_mark:|
+
+## Devices Regression Usage
 
 ```bash
-    run_regression.py (--help| -h)
-    run_regression.py [--device=<device>] [--run_dir=<run_dir_path>] [--mp=<num>]
+  run_regression.py (--help| -h)
+  run_regression.py [--device=<device>] [--run_dir=<run_dir_path>] [--mp=<num>]
 ```
 
 Example:
 
 ```bash
-    python3 run_regression.py --device_name=MOS --run_dir=test_mos
+  python3 run_regression.py --device_name=MOS --run_dir=test_mos
 ```
 
-### Options
+**Options**
 
 - `--help -h`                  Print this help message.
     
@@ -56,17 +109,48 @@ Example:
 - `--mp=<num>`                 The number of threads used in run.
 
 
-Another approach for testing LVS devices, you could make a full test for SG13G2 LVS rule deck, by executing the following command in current testing directory:
+Another approach for testing SG13G2 devices, you could make a full test for SG13G2 LVS rule deck, by executing the following command in current testing directory:
 
 ```bash
-make all
+  make test-LVS-main
 ```
 
+## Cells Regression Usage
+
+```bash
+  run_regression_cells.py (--help| -h)
+  run_regression_cells.py [--cell=<cell>] [--run_dir=<run_dir_path>] [--mp=<num>]
+```
+
+Example:
+
+```bash
+python3 run_regression_cells.py --cell=sg13g2_inv_1 --run_dir=test_inv
+```
+
+**Options**
+
+- `--help -h`                  Print this help message.
+    
+- `--cell=<cell>`              Specify the cell to run; all cells run if not specified.
+
+- `--run_dir=<run_dir_path>`   Run directory to save all the results [default: pwd]
+
+- `--mp=<num>`                 The number of threads used in run.
+
+
+Another approach for testing SG13G2 cells, you could make a full test for SG13G2 cells, by executing the following command in current testing directory:
+
+```bash
+  make test-LVS-cells
+```
+
+
 ## LVS Outputs
 
 You could find the regression run results at your run directory if you previously specified it through `--run_name=<run_name>`. Default path of run directory is `unit_tests_<date>_<time>` in the current testing directory.
 
-### Folder Structure of regression run results
+**Folder Structure of regression run results**
 
 ```text
 📁 unit_tests_<date>_<time>
@@ -81,36 +165,4 @@ You could find the regression run results at your run directory if you previousl
     ┣ 📜 <device_name>.lvsdb
  ```
 
-The outcome includes a database file for each device (`<device_name>.lvsdb`) containing LVS extractions and comparison results. You can view it by opening your gds file with: `klayout <device_name>.gds -mn <device_name>.lvsdb`. Alternatively, you can visualize it on your GDS file using the netlist browser option in the tools menu of the KLayout GUI as illustrated in the following figures.
-
-<p align="center">
-  <img src="../images/lvs_marker_1.png" width="40%" >
-</p>
-<p align="center">
-  Fig. 1. Netlist Browser for Klayout-LVS
-</p>
-
-After selecting Netlist Browser option, you could load the database file and visualize the LVS results.
-
-<p align="center">
-  <img src="../images/lvs_marker_2.png" width="70%" >
-</p>
-<p align="center">
-  Fig. 2. Loading LVS Netlist/database file - 1
-</p>
-
-<p align="center">
-  <img src="../images/lvs_marker_3.png" width="70%" >
-</p>
-<p align="center">
-  Fig. 3. Loading LVS Netlist/database file - 2
-</p>
-
-<p align="center">
-  <img src="../images/lvs_marker_4.png" width="70%" >
-</p>
-<p align="center">
-  Fig. 4. Visualize LVS results
-</p>
-
-Additionally, you can find the extracted netlist generated from your design at (`<device_name>_extracted.cir`) in the output run directory.
+The outcome includes a database file for each device (`<device_name>.lvsdb`) containing LVS extractions and comparison results. You can view it by opening your gds file with: `klayout <device_name>.gds -mn <device_name>.lvsdb`. Alternatively, you can visualize it on your GDS file using the netlist browser option in the tools menu of the KLayout GUI as illustrated in [LVS-Output](../README.md#lvs-outputs).
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py
index 0b0077cf..22da3f0a 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression.py
@@ -49,37 +49,6 @@
 SUPPORTED_SW_EXT = "yaml"
 
 
-def check_klayout_version():
-    """
-    Check klayout version and makes sure it would work with the LVS.
-    """
-    # ======= Checking Klayout version =======
-    klayout_v_ = os.popen("klayout -b -v").read()
-    klayout_v_ = klayout_v_.split("\n")[0]
-    klayout_v_list = []
-
-    if klayout_v_ == "":
-        logging.error("Klayout is not found. Please make sure klayout is installed.")
-        exit(1)
-    else:
-        klayout_v_list = [int(v) for v in klayout_v_.split(" ")[-1].split(".")]
-
-    if len(klayout_v_list) < 1 or len(klayout_v_list) > 3:
-        logging.error("Was not able to get klayout version properly.")
-        exit(1)
-    elif len(klayout_v_list) >= 2 or len(klayout_v_list) <= 3:
-        if klayout_v_list[1] < 28 or (
-            klayout_v_list[1] == 28 and klayout_v_list[2] <= 13
-        ):
-            logging.error("Prerequisites at a minimum: KLayout 0.28.14")
-            logging.error(
-                "Using this klayout version has not been assessed. Limits are unknown"
-            )
-            # exit(1)
-
-    logging.info(f"Your Klayout version is: {klayout_v_}")
-
-
 def parse_existing_devices(rule_deck_path, output_path, target_device_group=None):
     """
     This function collects the rule names from the existing lvs rule decks.
@@ -116,7 +85,7 @@ def parse_existing_devices(rule_deck_path, output_path, target_device_group=None
 
         lvs_files = [table_device_file]
 
-    rules_data = list()
+    dev_data = list()
 
     for runset in lvs_files:
         with open(runset, "r") as f:
@@ -129,11 +98,11 @@ def parse_existing_devices(rule_deck_path, output_path, target_device_group=None
                     )
                     rule_info["device_name"] = line_list[1]
                     rule_info["in_rule_deck"] = 1
-                    rules_data.append(rule_info)
+                    dev_data.append(rule_info)
 
-    df = pd.DataFrame(rules_data)
+    df = pd.DataFrame(dev_data)
     df.drop_duplicates(inplace=True)
-    df.to_csv(os.path.join(output_path, "rule_deck_rules.csv"), index=False)
+    df.to_csv(os.path.join(output_path, "rule_deck_devices.csv"), index=False)
     return df
 
 
@@ -367,7 +336,7 @@ def aggregate_results(results_df: pd.DataFrame, devices_df: pd.DataFrame):
     Parameters
     ----------
     results_df : pd.DataFrame
-        Dataframe that holds the information about the unit test rules.
+        Dataframe that holds the information about the unit test devices.
     devices_df : pd.DataFrame
         Dataframe that holds the information about all the devices implemented in the rule deck.
 
@@ -377,7 +346,7 @@ def aggregate_results(results_df: pd.DataFrame, devices_df: pd.DataFrame):
         A DataFrame that has all data analysis aggregated into one.
     """
     if len(devices_df) < 1 and len(results_df) < 1:
-        logging.error("There are no rules for analysis or run.")
+        logging.error("There are no devices for analysis or run.")
         exit(1)
     elif len(devices_df) < 1 and len(results_df) > 0:
         df = results_df
@@ -410,10 +379,10 @@ def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
     Returns
     -------
     bool
-        If all regression passed, it returns true. If any of the rules failed it returns false.
+        If all regression passed, it returns true. If any of the devices failed it returns false.
     """
 
-    # Parse Existing Rules
+    # Parse Existing devices
     devices_df = parse_existing_devices(lvs_dir, output_path, target_device_group)
     logging.info(
         "Total number of devices found in rule decks: {}".format(len(devices_df))
@@ -440,7 +409,7 @@ def run_regression(lvs_dir, output_path, target_device_group, cpu_count):
     # Generate error if there are any missing info or fails.
     df.to_csv(os.path.join(output_path, "all_test_cases_results.csv"), index=False)
 
-    # Check if there any rules that generated false positive or false negative
+    # Check if there any device that generated failure
     failing_results = df[~df["device_status"].isin(["Passed"])]
     logging.info("Failing test cases: \n" + str(failing_results))
 
@@ -467,7 +436,7 @@ def main(lvs_dir, output_path, target_device_group):
     Returns
     -------
     bool
-        If all regression passed, it returns true. If any of the rules failed it returns false.
+        If all regression passed, it returns true. If any of the devices failed it returns false.
     """
 
     # No. of threads
@@ -480,9 +449,6 @@ def main(lvs_dir, output_path, target_device_group):
     # Start of execution time
     t0 = time.time()
 
-    # Check Klayout version
-    check_klayout_version()
-
     # Calling regression function
     run_status = run_regression(lvs_dir, output_path, target_device_group, cpu_count)
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression_cells.py b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression_cells.py
new file mode 100644
index 00000000..aaa84499
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/run_regression_cells.py
@@ -0,0 +1,463 @@
+# ==========================================================================
+# Copyright 2024 IHP PDK Authors
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#    https://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+# ==========================================================================
+
+"""Run IHP 130nm BiCMOS Open Source PDK - SG13G2 LVS Regression For Cells.
+
+Usage:
+    run_regression_cells.py (--help| -h)
+    run_regression_cells.py [--cell=<cell>] [--run_dir=<run_dir_path>] [--mp=<num>]
+
+Options:
+    --help -h                 Print this help message.
+    --cell=<cell>             Specify the cell to run; all cells run if not specified.
+    --run_dir=<run_dir_path>  Run directory to save all the results [default: pwd]
+    --mp=<num>                The number of threads used in run.
+"""
+
+from subprocess import check_call
+import concurrent.futures
+import traceback
+import yaml
+from docopt import docopt
+import os
+from datetime import datetime
+import time
+import pandas as pd
+import logging
+import glob
+from pathlib import Path
+import shutil
+
+# CONSTANTS
+SUPPORTED_TC_EXT = "gds"
+SUPPORTED_SPICE_EXT = "cdl"
+SUPPORTED_SW_EXT = "yaml"
+
+
+def build_tests_dataframe(cells_dir, target_cell, cells):
+    """
+    Getting all test cases available in a formatted dataframe before running.
+
+    Parameters
+    ----------
+    cells_dir :  sting
+        Path string to the cells directory where all the testcases are located.
+    target_cell : str or None
+        Name of cell that we want to run regression for. If None, run all found.
+    cells : list
+        List that holds all available cells will be tested.
+
+    Returns
+    -------
+    pd.DataFrame
+        A DataFrame that has all the targeted test cases that we need to run.
+    """
+
+    # Construct df that holds all info
+    tc_df = pd.DataFrame({"cell_name": cells})
+
+    # Drop specific cell that has issues
+    values_to_drop = ["sg13g2_tiehi"]
+
+    # Drop rows where cell_name is in the list of values to drop
+    tc_df = tc_df[~tc_df['cell_name'].isin(values_to_drop)]
+
+    all_cells_layout = sorted(Path(cells_dir).rglob("*.{}".format(SUPPORTED_TC_EXT)))
+    all_cells_netlist = sorted(
+        Path(cells_dir).rglob("*.{}".format(SUPPORTED_SPICE_EXT))
+    )
+
+    # Mapping cell names to paths for both layout and netlist files
+    cell_paths = {
+        cell_name: {
+            "layout_path": next(
+                (path for path in all_cells_layout if cell_name in str(path)), None
+            ),
+            "netlist_path": next(
+                (path for path in all_cells_netlist if cell_name in str(path)), None
+            ),
+        }
+        for cell_name in tc_df["cell_name"]
+    }
+
+    # Adding paths to new columns in the DataFrame
+    tc_df[["layout_path", "netlist_path"]] = tc_df["cell_name"].apply(
+        lambda x: pd.Series(cell_paths[x])
+    )
+
+    # Print warning for cells without layout or netlist path
+    missing_cells = tc_df[
+        (tc_df["layout_path"].isnull()) | (tc_df["netlist_path"].isnull())
+    ]["cell_name"]
+    if not missing_cells.empty:
+        logging.warning(
+            "The following cells are missing layout (GDS) or netlist (CDL) files, or both: {}".format(
+                missing_cells.tolist()
+            )
+        )
+        logging.warning("These missing cells will be ignored in testing.")
+
+    # Drop missing cells
+    tc_df.drop(tc_df[tc_df["cell_name"].isin(missing_cells)].index, inplace=True)
+
+    # Check selected cell is available
+    if target_cell is not None:
+        tc_df = tc_df[tc_df["cell_name"] == target_cell]
+    if len(tc_df) < 1:
+        logging.error("No test cases remaining for selected cells after filtering.")
+        exit(1)
+
+    # info about available cells
+    logging.info("Total cells found: {}".format(len(tc_df)))
+    logging.info("Found cells: \n" + str(tc_df["cell_name"]))
+
+    tc_df["run_id"] = range(len(tc_df))
+
+    # Duplicate the original cells for iso/digisub
+    # iso_df = tc_df.copy()
+    sub_df = tc_df.copy()
+
+    # Add the suffix to each cell in the column
+    # iso_df["cell_name"] = iso_df["cell_name"] + "_iso"
+    sub_df["cell_name"] = sub_df["cell_name"] + "_digisub"
+
+    # Concatenate the original DataFrame with the modified DataFrame
+    # final_df = pd.concat([tc_df, iso_df, sub_df])
+    final_df = pd.concat([tc_df, sub_df])
+    final_df.reset_index(drop=True, inplace=True)
+
+    final_df["run_id"] = range(len(final_df))
+
+    return final_df
+
+
+def get_switches(yaml_file, rule_name):
+    """Parse yaml file and extract switches data
+    Parameters
+    ----------
+    yaml_file : str
+            yaml config file path given py the user.
+    Returns
+    -------
+    yaml_dic : dictionary
+            dictionary containing switches data.
+    """
+
+    # load yaml config data
+    with open(yaml_file, "r") as stream:
+        try:
+            yaml_dic = yaml.safe_load(stream)
+        except yaml.YAMLError as exc:
+            print(exc)
+
+    return [f"{param}={value}" for param, value in yaml_dic[rule_name].items()]
+
+
+def run_test_case(
+    lvs_dir, layout_path, netlist_path, run_dir, cell_name,
+):
+    """
+    This function run a single test case using the correct DRC file.
+
+    Parameters
+    ----------
+    lvs_dir : string or Path
+        Path to the location where all runsets exist.
+    layout_path : stirng or Path object
+        Path string to the layout of the test pattern we want to test.
+    netlist_path : stirng or Path object
+        Path string to the netlist of the test pattern we want to test.
+    run_dir : stirng or Path object
+        Path to the location where is the regression run is done.
+    cell_name : string
+        Cell name that we are running on.
+
+    Returns
+    -------
+    dict
+        A dict with all rule counts
+    """
+
+    # Get switches used for each run
+    sw_file = os.path.join(
+        Path(layout_path.parent).absolute(), f"{cell_name}.{SUPPORTED_SW_EXT}"
+    )
+
+    # Switches setup
+    if os.path.exists(sw_file):
+        switches = " ".join(get_switches(sw_file, cell_name))
+    else:
+        # Get switches
+        switches = ""  # default switch
+
+    # Creating run folder structure and copy testcases in it
+    pattern_clean = ".".join(os.path.basename(layout_path).split(".")[:-1])
+    output_loc = os.path.join(run_dir, cell_name)
+    pattern_log = os.path.join(output_loc, f"{pattern_clean}_lvs.log")
+    os.makedirs(output_loc, exist_ok=True)
+    layout_path_run = os.path.join(run_dir, cell_name, f"{cell_name}.gds")
+    netlist_path_run = os.path.join(run_dir, cell_name, f"{cell_name}.cdl")
+    shutil.copyfile(layout_path, layout_path_run)
+    shutil.copyfile(netlist_path, netlist_path_run)
+
+    # command to run LVS
+    call_str = (
+        f"python3 {lvs_dir}/run_lvs.py --layout={layout_path_run} --topcell={cell_name} "
+        f"--netlist={netlist_path_run} --run_dir={output_loc} {switches} > {pattern_log} 2>&1"
+    )
+
+    # Starting klayout run
+    try:
+        check_call(call_str, shell=True)
+    except Exception as e:
+        pattern_results = glob.glob(os.path.join(output_loc, f"{pattern_clean}*.lvsdb"))
+        if len(pattern_results) < 1:
+            logging.error("%s generated an exception: %s" % (pattern_clean, e))
+            traceback.print_exc()
+            raise Exception("Failed LVS run.")
+
+    # dumping log into output to make CI have the log
+    if os.path.isfile(pattern_log):
+        with open(pattern_log, "r") as f:
+            result = f.read()
+            for line in f:
+                line = line.strip()
+                logging.info(f"{line}")
+
+        # checking device status
+        cell_status = "Failed"
+        if "Congratulations! Netlists match" in result:
+            logging.info(f"{cell_name} testcase passed")
+            cell_status = "Passed"
+        else:
+            logging.error(f"{cell_name} testcase failed.")
+            logging.error(f"Please recheck {layout_path} and {netlist_path} files.")
+    else:
+        logging.error("Klayout LVS run failed, there is no log file is generated")
+        exit(1)
+
+    return cell_status
+
+
+def run_all_test_cases(tc_df: pd.DataFrame, lvs_dir, run_dir, num_workers):
+    """
+    This function run all test cases from the input dataframe.
+
+    Parameters
+    ----------
+    tc_df : pd.DataFrame
+        DataFrame that holds all the test cases information for running.
+    lvs_dir : string or Path
+        Path string to the location of the lvs runsets.
+    run_dir : string or Path
+        Path string to the location of the testing code and output.
+    num_workers : int
+        Number of workers to use for running the regression.
+
+    Returns
+    -------
+    pd.DataFrame
+        A pandas DataFrame with all test cases information post running.
+    """
+
+    tc_df["cell_status"] = "no status"
+
+    with concurrent.futures.ThreadPoolExecutor(max_workers=num_workers) as executor:
+        future_to_run_id = dict()
+        for _, row in tc_df.iterrows():
+            future_to_run_id[
+                executor.submit(
+                    run_test_case,
+                    lvs_dir,
+                    row["layout_path"],
+                    row["netlist_path"],
+                    run_dir,
+                    row["cell_name"],
+                )
+            ] = row["run_id"]
+
+        for future in concurrent.futures.as_completed(future_to_run_id):
+            run_id = future_to_run_id[future]
+            try:
+                tc_df.loc[tc_df["run_id"] == run_id, "cell_status"] = future.result()
+            except Exception as exc:
+                logging.error("%d generated an exception: %s" % (run_id, exc))
+                traceback.print_exc()
+                tc_df.loc[tc_df["run_id"] == run_id, "cell_status"] = "exception"
+
+    return tc_df
+
+
+def run_regression(lvs_dir, cells_dir, output_path, target_cell, cpu_count, cells):
+    """
+    Runs the full regression for std cells.
+
+    Parameters
+    ----------
+    lvs_dir : string
+        Path string to the LVS directory where all the LVS files are located.
+    cells_dir :  sting
+        Path string to the cells directory where all the testcases are located.
+    output_path : str
+        Path string to the location of the output results of the run.
+    target_cell : str or None
+        Name of cell that we want to run regression for. If None, run all found.
+    cpu_count : int
+        Number of cpu cores to be used in running testcases.
+    cells : list
+        List that holds all available cells will be tested.
+    Returns
+    -------
+    bool
+        If all regression passed, it returns true. If any of the cells failed it returns false.
+    """
+
+    # Get all test cases available in the repo.
+    tc_df = build_tests_dataframe(cells_dir, target_cell, cells)
+
+    # Run all test cases.
+    results_df = run_all_test_cases(tc_df, lvs_dir, output_path, cpu_count)
+    results_df.drop_duplicates(inplace=True)
+    results_df.drop("run_id", inplace=True, axis=1)
+    logging.info("Final results table: \n" + str(results_df))
+
+    # Generate error if there are any missing info or fails.
+    results_df.to_csv(
+        os.path.join(output_path, "all_test_cases_results.csv"), index=False
+    )
+
+    # Check if there any cell that generated failure
+    failing_results = results_df[~results_df["cell_status"].isin(["Passed"])]
+    logging.info("Failing test cases: \n" + str(failing_results))
+
+    if len(failing_results) > 0:
+        logging.error("Some test cases failed .....")
+        return False
+    else:
+        logging.info("All testcases passed.")
+        return True
+
+
+def main(lvs_dir, cells_dir, output_path, target_cell, cells):
+    """
+    Main function to run LVS regression for SG13G2 std cells.
+
+    Parameters
+    ----------
+    lvs_dir : str
+        Path string to the LVS directory where all the LVS files are located.
+    cells_dir :  sting
+        Path string to the cells directory where all the testcases are located.
+    output_path : str
+        Path string to the location of the output results of the run.
+    target_cell : str or None
+        Name of cell that we want to run regression for. If None, run all found.
+    cells : list
+        List that holds all available cells will be tested
+    Returns
+    -------
+    bool
+        If all regression passed, it returns true. If any of the cells failed it returns false.
+    """
+
+    # No. of threads
+    cpu_count = os.cpu_count() if args["--mp"] is None else int(args["--mp"])
+
+    # info logs for args
+    logging.info("Run folder is: {}".format(output_path))
+    logging.info("Target cell is: {}".format(target_cell))
+
+    # Start of execution time
+    t0 = time.time()
+
+    # Calling regression function
+    run_status = run_regression(
+        lvs_dir, cells_dir, output_path, target_cell, cpu_count, cells
+    )
+
+    #  End of execution time
+    logging.info("Total execution time {}s".format(time.time() - t0))
+
+    if run_status:
+        logging.info("Test completed successfully.")
+    else:
+        logging.error("Test failed.")
+        exit(1)
+
+
+if __name__ == "__main__":
+
+    # docopt setup
+    args = docopt(__doc__, version="LVS Regression: 0.2")
+
+    # default run name
+    run_name = datetime.utcnow().strftime("cells_tests_%Y_%m_%d_%H_%M_%S")
+
+    # args setup
+    run_dir = args["--run_dir"]
+    if run_dir == "pwd" or run_dir == "" or run_dir is None:
+        output_path = os.path.join(os.path.abspath(os.getcwd()), run_name)
+    else:
+        output_path = os.path.abspath(run_dir)
+
+    # Creating output dir
+    os.makedirs(output_path, exist_ok=True)
+
+    # Paths of regression dirs
+    testing_dir = os.path.dirname(os.path.abspath(__file__))
+    lvs_dir = os.path.dirname(testing_dir)
+
+    # logs format
+    logging.basicConfig(
+        level=logging.DEBUG,
+        handlers=[
+            logging.FileHandler(os.path.join(output_path, "{}.log".format(run_name))),
+            logging.StreamHandler(),
+        ],
+        format="%(asctime)s | %(levelname)-7s | %(message)s",
+        datefmt="%d-%b-%Y %H:%M:%S",
+    )
+
+    # Pandas setup
+    pd.set_option("display.max_columns", None)
+    pd.set_option("display.max_rows", None)
+    pd.set_option("max_colwidth", None)
+    pd.set_option("display.width", 1000)
+
+    # Available cells
+    cells_dir = os.path.join(testing_dir, "testcases", "sg13g2_cells")
+    if not os.path.isdir(cells_dir):
+        logging.error("Cells tests directory doesn't exist, please recheck")
+        logging.error(f"{cells_dir} path doesn't exist")
+        exit(1)
+
+    cells = [cell.name for cell in os.scandir(cells_dir) if cell.is_dir()]
+
+    # Make sure that we have std cells
+    if len(cells) < 1:
+        logging.error(f"There are no cells exist in {cells_dir}, please recheck")
+        exit(1)
+
+    # selected cell
+    target_cell = args["--cell"]
+    if target_cell and (target_cell not in cells):
+        logging.error("Selected cell doesn't exist, please recheck.")
+        logging.info(f"Allowed cells are {cells}")
+        exit(1)
+
+    # Calling main function
+    main(lvs_dir, cells_dir, output_path, target_cell, cells)
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/layout/sg13g2_a21o_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/layout/sg13g2_a21o_1.gds
new file mode 100644
index 00000000..ea7daa96
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/layout/sg13g2_a21o_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/netlist/sg13g2_a21o_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/netlist/sg13g2_a21o_1.cdl
new file mode 100644
index 00000000..e6de1edc
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_1/netlist/sg13g2_a21o_1.cdl
@@ -0,0 +1,79 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* 
+* Copyright 2023 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a21o_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a21o_1 A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21o_1_iso A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21o_1_digisub A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/layout/sg13g2_a21o_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/layout/sg13g2_a21o_2.gds
new file mode 100644
index 00000000..2f0127d2
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/layout/sg13g2_a21o_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/netlist/sg13g2_a21o_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/netlist/sg13g2_a21o_2.cdl
new file mode 100644
index 00000000..ece9caaa
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21o_2/netlist/sg13g2_a21o_2.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a21o_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a21o_2 A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21o_2_iso A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21o_2_digisub A1 A2 B1 VDD VSS X
+*.PININFO A1:I A2:I B1:I X:O VDD:B VSS:B
+MN0 net1 A1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net2 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net1 B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 B1 net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net3 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net3 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/layout/sg13g2_a21oi_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/layout/sg13g2_a21oi_1.gds
new file mode 100644
index 00000000..e24b6a0f
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/layout/sg13g2_a21oi_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/netlist/sg13g2_a21oi_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/netlist/sg13g2_a21oi_1.cdl
new file mode 100644
index 00000000..bbc58a72
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_1/netlist/sg13g2_a21oi_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a21oi_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a21oi_1 A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21oi_1_iso A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21oi_1_digisub A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/layout/sg13g2_a21oi_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/layout/sg13g2_a21oi_2.gds
new file mode 100644
index 00000000..2474b7b5
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/layout/sg13g2_a21oi_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/netlist/sg13g2_a21oi_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/netlist/sg13g2_a21oi_2.cdl
new file mode 100644
index 00000000..4589e4de
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a21oi_2/netlist/sg13g2_a21oi_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a21oi_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a21oi_2 A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21oi_2_iso A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a21oi_2_digisub A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MMNB0 Y B1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MMPB0 Y B1 pndA VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/layout/sg13g2_a221oi_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/layout/sg13g2_a221oi_1.gds
new file mode 100644
index 00000000..c44e8f43
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/layout/sg13g2_a221oi_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/netlist/sg13g2_a221oi_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/netlist/sg13g2_a221oi_1.cdl
new file mode 100644
index 00000000..96f97cbf
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a221oi_1/netlist/sg13g2_a221oi_1.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a221oi_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a221oi_1 A1 A2 B1 B2 C1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I C1:I Y:O VDD:B VSS:B
+MMPC0 Y C1 pndB VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB1 pndB B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 pndB B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMNC0 Y C1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB1 sndB1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 sndB1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a221oi_1_iso A1 A2 B1 B2 C1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I C1:I Y:O VDD:B VSS:B
+MMPC0 Y C1 pndB VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB1 pndB B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 pndB B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMNC0 Y C1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB1 sndB1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 sndB1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a221oi_1_digisub A1 A2 B1 B2 C1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I C1:I Y:O VDD:B VSS:B
+MMPC0 Y C1 pndB VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB1 pndB B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 pndB B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMNC0 Y C1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB1 sndB1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 sndB1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/layout/sg13g2_a22oi_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/layout/sg13g2_a22oi_1.gds
new file mode 100644
index 00000000..f8903cfb
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/layout/sg13g2_a22oi_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/netlist/sg13g2_a22oi_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/netlist/sg13g2_a22oi_1.cdl
new file mode 100644
index 00000000..aa167475
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_a22oi_1/netlist/sg13g2_a22oi_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_a22oi_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_a22oi_1 A1 A2 B1 B2 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I Y:O VDD:B VSS:B
+MN3 net1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP3 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 Y B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a22oi_1_iso A1 A2 B1 B2 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I Y:O VDD:B VSS:B
+MN3 net1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP3 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 Y B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_a22oi_1_digisub A1 A2 B1 B2 VDD VSS Y
+*.PININFO A1:I A2:I B1:I B2:I Y:O VDD:B VSS:B
+MN3 net1 B2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNB0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA1 sndA1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MMNA0 Y A1 sndA1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP3 Y B1 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPB0 Y B2 pndA VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA1 pndA A2 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MMPA0 pndA A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/layout/sg13g2_and2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/layout/sg13g2_and2_1.gds
new file mode 100644
index 00000000..4c8feefe
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/layout/sg13g2_and2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/netlist/sg13g2_and2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/netlist/sg13g2_and2_1.cdl
new file mode 100644
index 00000000..f059961c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_1/netlist/sg13g2_and2_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and2_1 A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and2_1_iso A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and2_1_digisub A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/layout/sg13g2_and2_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/layout/sg13g2_and2_2.gds
new file mode 100644
index 00000000..981e58d7
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/layout/sg13g2_and2_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/netlist/sg13g2_and2_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/netlist/sg13g2_and2_2.cdl
new file mode 100644
index 00000000..d7d7f050
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and2_2/netlist/sg13g2_and2_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and2_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and2_2 A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and2_2_iso A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and2_2_digisub A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net4 A net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net4 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 net2 B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 net4 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD net4 X VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net4 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/layout/sg13g2_and3_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/layout/sg13g2_and3_1.gds
new file mode 100644
index 00000000..d9c054af
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/layout/sg13g2_and3_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/netlist/sg13g2_and3_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/netlist/sg13g2_and3_1.cdl
new file mode 100644
index 00000000..f3f84cd1
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_1/netlist/sg13g2_and3_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and3_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and3_1 A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and3_1_iso A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and3_1_digisub A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/layout/sg13g2_and3_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/layout/sg13g2_and3_2.gds
new file mode 100644
index 00000000..de18620f
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/layout/sg13g2_and3_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/netlist/sg13g2_and3_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/netlist/sg13g2_and3_2.cdl
new file mode 100644
index 00000000..a520a156
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and3_2/netlist/sg13g2_and3_2.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and3_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and3_2 A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and3_2_iso A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and3_2_digisub A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net3 C VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 net2 A net1 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX6 net1 B net3 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX3 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 net2 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 net2 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 net2 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/layout/sg13g2_and4_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/layout/sg13g2_and4_1.gds
new file mode 100644
index 00000000..ecbcd298
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/layout/sg13g2_and4_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/netlist/sg13g2_and4_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/netlist/sg13g2_and4_1.cdl
new file mode 100644
index 00000000..cd876e71
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_1/netlist/sg13g2_and4_1.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and4_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and4_1 A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and4_1_iso A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and4_1_digisub A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/layout/sg13g2_and4_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/layout/sg13g2_and4_2.gds
new file mode 100644
index 00000000..0a01c43e
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/layout/sg13g2_and4_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/netlist/sg13g2_and4_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/netlist/sg13g2_and4_2.cdl
new file mode 100644
index 00000000..32dc9593
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_and4_2/netlist/sg13g2_and4_2.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_and4_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_and4_2 A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and4_2_iso A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_and4_2_digisub A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 net17 D VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net16 C net17 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 net15 B net16 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 net1 A net15 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP4 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net1 D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net1 C VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/layout/sg13g2_antennanp.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/layout/sg13g2_antennanp.gds
new file mode 100644
index 00000000..6376effd
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/layout/sg13g2_antennanp.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/netlist/sg13g2_antennanp.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/netlist/sg13g2_antennanp.cdl
new file mode 100644
index 00000000..555a32a7
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_antennanp/netlist/sg13g2_antennanp.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_antennanp
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_antennanp A VDD VSS
+*.PININFO A:I VDD:B VSS:B
+Ddn_1 VSS A dantenna m=1 w=780n l=780n a=608.4f p=3.12u
+DD0 A VDD dpantenna m=1 w=1.05u l=1.34u a=1.407p p=4.78u
+.ENDS
+
+.SUBCKT sg13g2_antennanp_iso A VDD VSS
+*.PININFO A:I VDD:B VSS:B
+Ddn_1 VSS A dantenna m=1 w=780n l=780n a=608.4f p=3.12u
+DD0 A VDD dpantenna m=1 w=1.05u l=1.34u a=1.407p p=4.78u
+.ENDS
+
+.SUBCKT sg13g2_antennanp_digisub A VDD VSS
+*.PININFO A:I VDD:B VSS:B
+Ddn_1 VSS A dantenna m=1 w=780n l=780n a=608.4f p=3.12u
+DD0 A VDD dpantenna m=1 w=1.05u l=1.34u a=1.407p p=4.78u
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/layout/sg13g2_buf_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/layout/sg13g2_buf_1.gds
new file mode 100644
index 00000000..1f8fa5dc
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/layout/sg13g2_buf_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/netlist/sg13g2_buf_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/netlist/sg13g2_buf_1.cdl
new file mode 100644
index 00000000..7e374cdb
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_1/netlist/sg13g2_buf_1.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_buf_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_buf_1 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_buf_1_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_buf_1_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/layout/sg13g2_buf_16.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/layout/sg13g2_buf_16.gds
new file mode 100644
index 00000000..d063da2c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/layout/sg13g2_buf_16.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/netlist/sg13g2_buf_16.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/netlist/sg13g2_buf_16.cdl
new file mode 100644
index 00000000..b59b8f40
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_16/netlist/sg13g2_buf_16.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_buf_16
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_buf_16 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=4.44u l=130.00n ng=6
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=6.72u l=130.00n ng=6
+.ENDS
+
+.SUBCKT sg13g2_buf_16_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=4.44u l=130.00n ng=6
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=6.72u l=130.00n ng=6
+.ENDS
+
+.SUBCKT sg13g2_buf_16_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=4.44u l=130.00n ng=6
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=11.84u l=130.00n ng=16
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=17.92u l=130.00n ng=16
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=6.72u l=130.00n ng=6
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/layout/sg13g2_buf_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/layout/sg13g2_buf_2.gds
new file mode 100644
index 00000000..380913af
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/layout/sg13g2_buf_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/netlist/sg13g2_buf_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/netlist/sg13g2_buf_2.cdl
new file mode 100644
index 00000000..3cde48fb
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_2/netlist/sg13g2_buf_2.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_buf_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_buf_2 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_buf_2_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_buf_2_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/layout/sg13g2_buf_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/layout/sg13g2_buf_4.gds
new file mode 100644
index 00000000..1b1b08b5
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/layout/sg13g2_buf_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/netlist/sg13g2_buf_4.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/netlist/sg13g2_buf_4.cdl
new file mode 100644
index 00000000..a7ce7675
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_4/netlist/sg13g2_buf_4.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_buf_4
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_buf_4 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.68u l=130.00n ng=2
+.ENDS
+
+.SUBCKT sg13g2_buf_4_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.68u l=130.00n ng=2
+.ENDS
+
+.SUBCKT sg13g2_buf_4_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=2.96u l=130.00n ng=4
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=4.48u l=130.00n ng=4
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.68u l=130.00n ng=2
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/layout/sg13g2_buf_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/layout/sg13g2_buf_8.gds
new file mode 100644
index 00000000..1436fb2a
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/layout/sg13g2_buf_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/netlist/sg13g2_buf_8.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/netlist/sg13g2_buf_8.cdl
new file mode 100644
index 00000000..0ea2191b
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_buf_8/netlist/sg13g2_buf_8.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_buf_8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_buf_8 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=2.22u l=130.00n ng=3
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=3.36u l=130.00n ng=3
+.ENDS
+
+.SUBCKT sg13g2_buf_8_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=2.22u l=130.00n ng=3
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=3.36u l=130.00n ng=3
+.ENDS
+
+.SUBCKT sg13g2_buf_8_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MN1 net1 A VSS VSS sg13_lv_nmos m=1 w=2.22u l=130.00n ng=3
+MN0 X net1 VSS VSS sg13_lv_nmos m=1 w=5.92u l=130.00n ng=8
+MP1 X net1 VDD VDD sg13_lv_pmos m=1 w=8.96u l=130.00n ng=8
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=3.36u l=130.00n ng=3
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/layout/sg13g2_decap_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/layout/sg13g2_decap_4.gds
new file mode 100644
index 00000000..c5779d11
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/layout/sg13g2_decap_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/netlist/sg13g2_decap_4.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/netlist/sg13g2_decap_4.cdl
new file mode 100644
index 00000000..ad190677
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_4/netlist/sg13g2_decap_4.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_decap_4
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_decap_4 VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=1 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1
+.ENDS
+
+.SUBCKT sg13g2_decap_4_iso VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=1 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1
+.ENDS
+
+.SUBCKT sg13g2_decap_4_digisub VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=1 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=1 w=1.000u l=1.000u ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/layout/sg13g2_decap_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/layout/sg13g2_decap_8.gds
new file mode 100644
index 00000000..965cb12f
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/layout/sg13g2_decap_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/netlist/sg13g2_decap_8.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/netlist/sg13g2_decap_8.cdl
new file mode 100644
index 00000000..16a45ffc
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_decap_8/netlist/sg13g2_decap_8.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_decap_8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_decap_8 VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=2 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=2 w=1.000u l=1.000u ng=1
+.ENDS
+
+.SUBCKT sg13g2_decap_8_iso VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=2 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=2 w=1.000u l=1.000u ng=1
+.ENDS
+
+.SUBCKT sg13g2_decap_8_digisub VDD VSS
+*.PININFO VDD:B VSS:B
+MX1 VSS VDD VSS VSS sg13_lv_nmos m=2 w=420.00n l=1.000u ng=1
+MX0 VDD VSS VDD VDD sg13_lv_pmos m=2 w=1.000u l=1.000u ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/layout/sg13g2_dfrbp_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/layout/sg13g2_dfrbp_1.gds
new file mode 100644
index 00000000..6a19bab1
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/layout/sg13g2_dfrbp_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/netlist/sg13g2_dfrbp_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/netlist/sg13g2_dfrbp_1.cdl
new file mode 100644
index 00000000..351cb130
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_1/netlist/sg13g2_dfrbp_1.cdl
@@ -0,0 +1,139 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dfrbp_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dfrbp_1 CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dfrbp_1_iso CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dfrbp_1_digisub CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/layout/sg13g2_dfrbp_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/layout/sg13g2_dfrbp_2.gds
new file mode 100644
index 00000000..c892663d
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/layout/sg13g2_dfrbp_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/netlist/sg13g2_dfrbp_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/netlist/sg13g2_dfrbp_2.cdl
new file mode 100644
index 00000000..304d94d3
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dfrbp_2/netlist/sg13g2_dfrbp_2.cdl
@@ -0,0 +1,139 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dfrbp_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dfrbp_2 CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dfrbp_2_iso CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dfrbp_2_digisub CLK D Q Q_N RESET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MN13 net12 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN14 net5 clkneg net12 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN15 net2 net5 net11 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN16 net11 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN6 Q_N net5 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Db D net10 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net10 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN7 Db clkneg net6 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN8 net6 clkpos net9 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN9 net9 net4 net8 VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN10 net8 RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN11 net4 net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 clkneg CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN12 net4 clkpos net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 clkpos clkneg VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN4 Q net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 net1 net5 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP14 net5 clkpos net3 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP15 net2 net5 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP16 net2 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP6 Q_N net5 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP7 Db clkpos net6 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP0 Db RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP1 Db D VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP8 net7 net4 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP9 net6 clkneg net7 VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP10 net6 RESET_B VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP2 clkneg CLK VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 clkpos clkneg VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP11 net4 net6 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP12 net4 clkneg net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 Q net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP13 net3 net2 VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MP5 net1 net5 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/layout/sg13g2_dlhq_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/layout/sg13g2_dlhq_1.gds
new file mode 100644
index 00000000..d98c36a5
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/layout/sg13g2_dlhq_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/netlist/sg13g2_dlhq_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/netlist/sg13g2_dlhq_1.cdl
new file mode 100644
index 00000000..b0b49bd0
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhq_1/netlist/sg13g2_dlhq_1.cdl
@@ -0,0 +1,103 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlhq_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlhq_1 D GATE Q VDD VSS
+*.PININFO D:I GATE:I Q:O VDD:B VSS:B
+MX17 VDD a_386_326_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX16 a_592_149_ a_685_59_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_386_326_ a_592_149_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX12 VDD D a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX9 a_562_123_ GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_562_123_ a_685_59_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD a_386_326_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_229_392_ a_562_123_ a_592_149_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX1 a_229_392_ a_116_424_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX15 a_562_123_ GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 VSS a_562_123_ a_685_59_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_514_149_ a_562_123_ a_592_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX10 VSS a_386_326_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 a_239_85_ a_116_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 VSS a_386_326_ a_514_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_386_326_ a_592_149_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 a_592_149_ a_685_59_ a_239_85_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX0 VSS D a_116_424_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhq_1_iso D GATE Q VDD VSS
+*.PININFO D:I GATE:I Q:O VDD:B VSS:B
+MX17 VDD a_386_326_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX16 a_592_149_ a_685_59_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_386_326_ a_592_149_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX12 VDD D a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX9 a_562_123_ GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_562_123_ a_685_59_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD a_386_326_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_229_392_ a_562_123_ a_592_149_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX1 a_229_392_ a_116_424_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX15 a_562_123_ GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 VSS a_562_123_ a_685_59_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_514_149_ a_562_123_ a_592_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX10 VSS a_386_326_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 a_239_85_ a_116_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 VSS a_386_326_ a_514_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_386_326_ a_592_149_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 a_592_149_ a_685_59_ a_239_85_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX0 VSS D a_116_424_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhq_1_digisub D GATE Q VDD VSS
+*.PININFO D:I GATE:I Q:O VDD:B VSS:B
+MX17 VDD a_386_326_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX16 a_592_149_ a_685_59_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_386_326_ a_592_149_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX12 VDD D a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX9 a_562_123_ GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_562_123_ a_685_59_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX4 VDD a_386_326_ a_419_392_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_229_392_ a_562_123_ a_592_149_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX1 a_229_392_ a_116_424_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX15 a_562_123_ GATE VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 VSS a_562_123_ a_685_59_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_514_149_ a_562_123_ a_592_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX10 VSS a_386_326_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 a_239_85_ a_116_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 VSS a_386_326_ a_514_149_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_386_326_ a_592_149_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 a_592_149_ a_685_59_ a_239_85_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX0 VSS D a_116_424_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/layout/sg13g2_dlhr_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/layout/sg13g2_dlhr_1.gds
new file mode 100644
index 00000000..a4144bf3
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/layout/sg13g2_dlhr_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/netlist/sg13g2_dlhr_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/netlist/sg13g2_dlhr_1.cdl
new file mode 100644
index 00000000..e93acebb
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhr_1/netlist/sg13g2_dlhr_1.cdl
@@ -0,0 +1,124 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlhr_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlhr_1 D GATE Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MX0 a_823_98_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 VDD a_823_98_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX15 a_642_392_ a_353_98_ a_753_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX6 a_753_508_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_564_392_ a_226_104_ a_642_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX18 VDD a_27_142_ a_564_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_27_142_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD GATE a_226_104_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 VDD a_1342_74_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 VDD a_642_392_ a_823_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX20 a_353_98_ a_226_104_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_1342_74_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_823_98_ a_642_392_ a_1051_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX21 a_1051_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_642_392_ a_226_104_ a_775_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_775_124_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX7 VSS a_823_98_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_571_80_ a_353_98_ a_642_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX23 VSS a_27_142_ a_571_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX4 a_27_142_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX19 VSS GATE a_226_104_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 VSS a_1342_74_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 a_353_98_ a_226_104_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_1342_74_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhr_1_iso D GATE Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MX0 a_823_98_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 VDD a_823_98_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX15 a_642_392_ a_353_98_ a_753_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX6 a_753_508_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_564_392_ a_226_104_ a_642_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX18 VDD a_27_142_ a_564_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_27_142_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD GATE a_226_104_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 VDD a_1342_74_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 VDD a_642_392_ a_823_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX20 a_353_98_ a_226_104_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_1342_74_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_823_98_ a_642_392_ a_1051_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX21 a_1051_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_642_392_ a_226_104_ a_775_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_775_124_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX7 VSS a_823_98_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_571_80_ a_353_98_ a_642_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX23 VSS a_27_142_ a_571_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX4 a_27_142_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX19 VSS GATE a_226_104_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 VSS a_1342_74_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 a_353_98_ a_226_104_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_1342_74_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhr_1_digisub D GATE Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O Q_N:O VDD:B VSS:B
+MX0 a_823_98_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 VDD a_823_98_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX15 a_642_392_ a_353_98_ a_753_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX6 a_753_508_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_564_392_ a_226_104_ a_642_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX18 VDD a_27_142_ a_564_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_27_142_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD GATE a_226_104_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 VDD a_1342_74_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 VDD a_642_392_ a_823_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX20 a_353_98_ a_226_104_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_1342_74_ a_823_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_823_98_ a_642_392_ a_1051_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX21 a_1051_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX11 a_642_392_ a_226_104_ a_775_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 a_775_124_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX7 VSS a_823_98_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_571_80_ a_353_98_ a_642_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX23 VSS a_27_142_ a_571_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX4 a_27_142_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX19 VSS GATE a_226_104_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 VSS a_1342_74_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 a_353_98_ a_226_104_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_1342_74_ a_823_98_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/layout/sg13g2_dlhrq_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/layout/sg13g2_dlhrq_1.gds
new file mode 100644
index 00000000..a31805ce
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/layout/sg13g2_dlhrq_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/netlist/sg13g2_dlhrq_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/netlist/sg13g2_dlhrq_1.cdl
new file mode 100644
index 00000000..783a9f24
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlhrq_1/netlist/sg13g2_dlhrq_1.cdl
@@ -0,0 +1,112 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlhrq_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlhrq_1 D GATE Q RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O VDD:B VSS:B
+MX19 a_769_74_ a_817_48_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX14 a_565_74_ a_363_74_ a_643_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX11 VSS a_817_48_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX10 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX8 a_1045_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 a_817_48_ a_643_74_ a_1045_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX6 a_643_74_ a_216_424_ a_769_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 VSS GATE a_216_424_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 VSS a_27_424_ a_565_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 a_363_74_ a_216_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VDD a_643_74_ a_817_48_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD a_27_424_ a_568_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX16 a_643_74_ a_363_74_ a_759_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX15 VDD GATE a_216_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_759_508_ a_817_48_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 a_363_74_ a_216_424_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD a_817_48_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_817_48_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX0 a_568_392_ a_216_424_ a_643_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhrq_1_iso D GATE Q RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O VDD:B VSS:B
+MX19 a_769_74_ a_817_48_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX14 a_565_74_ a_363_74_ a_643_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX11 VSS a_817_48_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX10 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX8 a_1045_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 a_817_48_ a_643_74_ a_1045_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX6 a_643_74_ a_216_424_ a_769_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 VSS GATE a_216_424_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 VSS a_27_424_ a_565_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 a_363_74_ a_216_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VDD a_643_74_ a_817_48_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD a_27_424_ a_568_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX16 a_643_74_ a_363_74_ a_759_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX15 VDD GATE a_216_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_759_508_ a_817_48_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 a_363_74_ a_216_424_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD a_817_48_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_817_48_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX0 a_568_392_ a_216_424_ a_643_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlhrq_1_digisub D GATE Q RESET_B VDD VSS
+*.PININFO D:I GATE:I RESET_B:I Q:O VDD:B VSS:B
+MX19 a_769_74_ a_817_48_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX14 a_565_74_ a_363_74_ a_643_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX11 VSS a_817_48_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX10 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX8 a_1045_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 a_817_48_ a_643_74_ a_1045_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX6 a_643_74_ a_216_424_ a_769_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 VSS GATE a_216_424_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 VSS a_27_424_ a_565_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX1 a_363_74_ a_216_424_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VDD a_643_74_ a_817_48_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD a_27_424_ a_568_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX16 a_643_74_ a_363_74_ a_759_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX15 VDD GATE a_216_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX12 a_759_508_ a_817_48_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 a_363_74_ a_216_424_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 VDD a_817_48_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_817_48_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX0 a_568_392_ a_216_424_ a_643_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/layout/sg13g2_dllr_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/layout/sg13g2_dllr_1.gds
new file mode 100644
index 00000000..68b8652c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/layout/sg13g2_dllr_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/netlist/sg13g2_dllr_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/netlist/sg13g2_dllr_1.cdl
new file mode 100644
index 00000000..7a8e25b4
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllr_1/netlist/sg13g2_dllr_1.cdl
@@ -0,0 +1,118 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dllr_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dllr_1 D GATE_N Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE_N:I Q:I RESET_B:I Q_N:O VDD:B VSS:B
+MX19 VDD a_686_74_ a_889_92_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX17 a_802_508_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX16 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 VDD a_27_424_ a_611_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX10 a_889_92_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 a_686_74_ a_231_74_ a_802_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX7 VDD GATE_N a_231_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1437_112_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_611_392_ a_373_74_ a_686_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 VDD a_889_92_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_373_74_ a_231_74_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 VDD a_1437_112_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX23 VSS a_1437_112_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_373_74_ a_231_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX21 a_889_92_ a_686_74_ a_1133_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX20 VSS GATE_N a_231_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_1437_112_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX14 a_841_118_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX13 VSS a_27_424_ a_608_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_686_74_ a_373_74_ a_841_118_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX8 VSS a_889_92_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_608_74_ a_231_74_ a_686_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_1133_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dllr_1_iso D GATE_N Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE_N:I Q:I RESET_B:I Q_N:O VDD:B VSS:B
+MX19 VDD a_686_74_ a_889_92_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX17 a_802_508_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX16 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 VDD a_27_424_ a_611_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX10 a_889_92_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 a_686_74_ a_231_74_ a_802_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX7 VDD GATE_N a_231_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1437_112_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_611_392_ a_373_74_ a_686_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 VDD a_889_92_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_373_74_ a_231_74_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 VDD a_1437_112_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX23 VSS a_1437_112_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_373_74_ a_231_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX21 a_889_92_ a_686_74_ a_1133_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX20 VSS GATE_N a_231_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_1437_112_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX14 a_841_118_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX13 VSS a_27_424_ a_608_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_686_74_ a_373_74_ a_841_118_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX8 VSS a_889_92_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_608_74_ a_231_74_ a_686_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_1133_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dllr_1_digisub D GATE_N Q Q_N RESET_B VDD VSS
+*.PININFO D:I GATE_N:I Q:I RESET_B:I Q_N:O VDD:B VSS:B
+MX19 VDD a_686_74_ a_889_92_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX17 a_802_508_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX16 a_27_424_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 VDD a_27_424_ a_611_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX10 a_889_92_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX9 a_686_74_ a_231_74_ a_802_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX7 VDD GATE_N a_231_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1437_112_ a_889_92_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_611_392_ a_373_74_ a_686_74_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 VDD a_889_92_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 a_373_74_ a_231_74_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 VDD a_1437_112_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX23 VSS a_1437_112_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX22 a_373_74_ a_231_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX21 a_889_92_ a_686_74_ a_1133_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX20 VSS GATE_N a_231_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_1437_112_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_27_424_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX14 a_841_118_ a_889_92_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX13 VSS a_27_424_ a_608_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_686_74_ a_373_74_ a_841_118_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX8 VSS a_889_92_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_608_74_ a_231_74_ a_686_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_1133_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/layout/sg13g2_dllrq_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/layout/sg13g2_dllrq_1.gds
new file mode 100644
index 00000000..f6b086c8
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/layout/sg13g2_dllrq_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/netlist/sg13g2_dllrq_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/netlist/sg13g2_dllrq_1.cdl
new file mode 100644
index 00000000..89b9e424
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dllrq_1/netlist/sg13g2_dllrq_1.cdl
@@ -0,0 +1,112 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dllrq_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dllrq_1 D GATE_N Q RESET_B VDD VSS
+*.PININFO D:I GATE_N:I RESET_B:I Q:O VDD:B VSS:B
+MX18 a_357_392_ a_232_98_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 VSS a_897_406_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_654_392_ a_357_392_ a_854_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 VSS a_27_136_ a_681_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_681_74_ a_232_98_ a_654_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_27_136_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX6 a_1139_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 a_854_74_ a_897_406_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_897_406_ a_654_392_ a_1139_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX1 VSS GATE_N a_232_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX19 VDD GATE_N a_232_98_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX15 a_897_406_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_654_392_ a_232_98_ a_793_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX11 a_793_508_ a_897_406_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 VDD a_897_406_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX8 a_27_136_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_27_136_ a_570_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 VDD a_654_392_ a_897_406_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 a_570_392_ a_357_392_ a_654_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX0 a_357_392_ a_232_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dllrq_1_iso D GATE_N Q RESET_B VDD VSS
+*.PININFO D:I GATE_N:I RESET_B:I Q:O VDD:B VSS:B
+MX18 a_357_392_ a_232_98_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 VSS a_897_406_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_654_392_ a_357_392_ a_854_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 VSS a_27_136_ a_681_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_681_74_ a_232_98_ a_654_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_27_136_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX6 a_1139_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 a_854_74_ a_897_406_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_897_406_ a_654_392_ a_1139_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX1 VSS GATE_N a_232_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX19 VDD GATE_N a_232_98_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX15 a_897_406_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_654_392_ a_232_98_ a_793_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX11 a_793_508_ a_897_406_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 VDD a_897_406_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX8 a_27_136_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_27_136_ a_570_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 VDD a_654_392_ a_897_406_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 a_570_392_ a_357_392_ a_654_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX0 a_357_392_ a_232_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dllrq_1_digisub D GATE_N Q RESET_B VDD VSS
+*.PININFO D:I GATE_N:I RESET_B:I Q:O VDD:B VSS:B
+MX18 a_357_392_ a_232_98_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX17 VSS a_897_406_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 a_654_392_ a_357_392_ a_854_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX14 VSS a_27_136_ a_681_74_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX12 a_681_74_ a_232_98_ a_654_392_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_27_136_ D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX6 a_1139_74_ RESET_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 a_854_74_ a_897_406_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX3 a_897_406_ a_654_392_ a_1139_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+MX1 VSS GATE_N a_232_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX19 VDD GATE_N a_232_98_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX15 a_897_406_ RESET_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX13 a_654_392_ a_232_98_ a_793_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX11 a_793_508_ a_897_406_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX10 VDD a_897_406_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX8 a_27_136_ D VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 VDD a_27_136_ a_570_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 VDD a_654_392_ a_897_406_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 a_570_392_ a_357_392_ a_654_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n 
++ ng=1
+MX0 a_357_392_ a_232_98_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/layout/sg13g2_dlygate4sd1_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/layout/sg13g2_dlygate4sd1_1.gds
new file mode 100644
index 00000000..9606c1cf
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/layout/sg13g2_dlygate4sd1_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/netlist/sg13g2_dlygate4sd1_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/netlist/sg13g2_dlygate4sd1_1.cdl
new file mode 100644
index 00000000..4efe296f
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd1_1/netlist/sg13g2_dlygate4sd1_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlygate4sd1_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlygate4sd1_1 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd1_1_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd1_1_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/layout/sg13g2_dlygate4sd2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/layout/sg13g2_dlygate4sd2_1.gds
new file mode 100644
index 00000000..db47ffa5
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/layout/sg13g2_dlygate4sd2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/netlist/sg13g2_dlygate4sd2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/netlist/sg13g2_dlygate4sd2_1.cdl
new file mode 100644
index 00000000..13e7ed57
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd2_1/netlist/sg13g2_dlygate4sd2_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlygate4sd2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlygate4sd2_1 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd2_1_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd2_1_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=250.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=180.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/layout/sg13g2_dlygate4sd3_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/layout/sg13g2_dlygate4sd3_1.gds
new file mode 100644
index 00000000..06dde2f6
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/layout/sg13g2_dlygate4sd3_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/netlist/sg13g2_dlygate4sd3_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/netlist/sg13g2_dlygate4sd3_1.cdl
new file mode 100644
index 00000000..247a92e3
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_dlygate4sd3_1/netlist/sg13g2_dlygate4sd3_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_dlygate4sd3_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_dlygate4sd3_1 A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd3_1_iso A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_dlygate4sd3_1_digisub A VDD VSS X
+*.PININFO A:I X:O VDD:B VSS:B
+MP3 X net3 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 net3 net2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=500.0n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MN3 X net3 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN1 net2 net1 VSS VSS sg13_lv_nmos m=1 w=420.00n l=500.0n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/layout/sg13g2_ebufn_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/layout/sg13g2_ebufn_2.gds
new file mode 100644
index 00000000..6e5ecb68
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/layout/sg13g2_ebufn_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/netlist/sg13g2_ebufn_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/netlist/sg13g2_ebufn_2.cdl
new file mode 100644
index 00000000..5ea95b04
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_2/netlist/sg13g2_ebufn_2.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_ebufn_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_ebufn_2 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net4 net3 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN2 Z net1 net4 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN1 net3 TE_B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP3 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP2 Z net1 net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP1 net3 TE_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_2_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net4 net3 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN2 Z net1 net4 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN1 net3 TE_B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP3 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP2 Z net1 net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP1 net3 TE_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_2_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net4 net3 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN2 Z net1 net4 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN1 net3 TE_B VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP3 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP2 Z net1 net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP1 net3 TE_B VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/layout/sg13g2_ebufn_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/layout/sg13g2_ebufn_4.gds
new file mode 100644
index 00000000..750ffeb2
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/layout/sg13g2_ebufn_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/netlist/sg13g2_ebufn_4.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/netlist/sg13g2_ebufn_4.cdl
new file mode 100644
index 00000000..45601c01
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_4/netlist/sg13g2_ebufn_4.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_ebufn_4
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_ebufn_4 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 net23 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net21 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 Z net23 net22 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN3 net22 net21 VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP0 net23 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net21 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 Z net23 net24 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_4_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 net23 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net21 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 Z net23 net22 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN3 net22 net21 VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP0 net23 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net21 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 Z net23 net24 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_4_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 net23 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net21 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 Z net23 net22 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN3 net22 net21 VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP0 net23 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net21 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP2 Z net23 net24 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/layout/sg13g2_ebufn_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/layout/sg13g2_ebufn_8.gds
new file mode 100644
index 00000000..92fa51c8
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/layout/sg13g2_ebufn_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/netlist/sg13g2_ebufn_8.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/netlist/sg13g2_ebufn_8.cdl
new file mode 100644
index 00000000..8a678d5e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_ebufn_8/netlist/sg13g2_ebufn_8.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_ebufn_8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_ebufn_8 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net23 net22 VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 Z net21 net23 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN1 net22 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net21 A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 Z net21 net24 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP1 net22 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net21 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_8_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net23 net22 VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 Z net21 net23 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN1 net22 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net21 A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 Z net21 net24 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP1 net22 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net21 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_ebufn_8_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN3 net23 net22 VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 Z net21 net23 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN1 net22 TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net21 A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP3 net24 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 Z net21 net24 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP1 net22 TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP0 net21 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/layout/sg13g2_einvn_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/layout/sg13g2_einvn_2.gds
new file mode 100644
index 00000000..76af37e6
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/layout/sg13g2_einvn_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/netlist/sg13g2_einvn_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/netlist/sg13g2_einvn_2.cdl
new file mode 100644
index 00000000..df1068f2
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_2/netlist/sg13g2_einvn_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_einvn_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_einvn_2 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net1 TE VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Z A net1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MP1 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Z A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_2_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net1 TE VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Z A net1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MP1 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Z A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_2_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MN1 net1 TE VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN0 Z A net1 VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MP1 net2 TE_B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Z A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/layout/sg13g2_einvn_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/layout/sg13g2_einvn_4.gds
new file mode 100644
index 00000000..efb51630
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/layout/sg13g2_einvn_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/netlist/sg13g2_einvn_4.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/netlist/sg13g2_einvn_4.cdl
new file mode 100644
index 00000000..830db64d
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_4/netlist/sg13g2_einvn_4.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_einvn_4
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_einvn_4 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN1 net16 TE VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Z A net16 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net17 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP0 Z A net17 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_4_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN1 net16 TE VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Z A net16 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net17 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP0 Z A net17 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_4_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN1 net16 TE VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Z A net16 VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net17 TE_B VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MP0 Z A net17 VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/layout/sg13g2_einvn_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/layout/sg13g2_einvn_8.gds
new file mode 100644
index 00000000..c0aa3a4d
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/layout/sg13g2_einvn_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/netlist/sg13g2_einvn_8.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/netlist/sg13g2_einvn_8.cdl
new file mode 100644
index 00000000..b4d41caa
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_einvn_8/netlist/sg13g2_einvn_8.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_einvn_8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_einvn_8 A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 Z A net29 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net29 TE VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MP1 net28 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP0 Z A net28 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_8_iso A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 Z A net29 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net29 TE VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MP1 net28 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP0 Z A net28 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_einvn_8_digisub A TE_B VDD VSS Z
+*.PININFO A:I TE_B:I Z:O VDD:B VSS:B
+MN0 Z A net29 VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MN2 TE TE_B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net29 TE VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MP1 net28 TE_B VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP0 Z A net28 VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+MP2 TE TE_B VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_1/layout/sg13g2_fill_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_1/layout/sg13g2_fill_1.gds
new file mode 100644
index 00000000..b58f1d45
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_1/layout/sg13g2_fill_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_2/layout/sg13g2_fill_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_2/layout/sg13g2_fill_2.gds
new file mode 100644
index 00000000..e7d9fb80
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_2/layout/sg13g2_fill_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_4/layout/sg13g2_fill_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_4/layout/sg13g2_fill_4.gds
new file mode 100644
index 00000000..a2b68de9
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_4/layout/sg13g2_fill_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_8/layout/sg13g2_fill_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_8/layout/sg13g2_fill_8.gds
new file mode 100644
index 00000000..9941096a
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_fill_8/layout/sg13g2_fill_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/layout/sg13g2_inv_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/layout/sg13g2_inv_1.gds
new file mode 100644
index 00000000..80e89cb5
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/layout/sg13g2_inv_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/netlist/sg13g2_inv_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/netlist/sg13g2_inv_1.cdl
new file mode 100644
index 00000000..0b85b155
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_1/netlist/sg13g2_inv_1.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_inv_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_inv_1 A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_1_iso A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_1_digisub A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/layout/sg13g2_inv_16.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/layout/sg13g2_inv_16.gds
new file mode 100644
index 00000000..b44d8537
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/layout/sg13g2_inv_16.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/netlist/sg13g2_inv_16.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/netlist/sg13g2_inv_16.cdl
new file mode 100644
index 00000000..96cf3839
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_16/netlist/sg13g2_inv_16.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_inv_16
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_inv_16 A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=16 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=16 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_16_iso A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=16 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=16 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_16_digisub A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=16 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=16 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/layout/sg13g2_inv_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/layout/sg13g2_inv_2.gds
new file mode 100644
index 00000000..79b63e71
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/layout/sg13g2_inv_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/netlist/sg13g2_inv_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/netlist/sg13g2_inv_2.cdl
new file mode 100644
index 00000000..536b8287
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_2/netlist/sg13g2_inv_2.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_inv_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_inv_2 A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_2_iso A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_2_digisub A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/layout/sg13g2_inv_4.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/layout/sg13g2_inv_4.gds
new file mode 100644
index 00000000..2714ae4e
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/layout/sg13g2_inv_4.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/netlist/sg13g2_inv_4.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/netlist/sg13g2_inv_4.cdl
new file mode 100644
index 00000000..4d26a1f4
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_4/netlist/sg13g2_inv_4.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_inv_4
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_inv_4 A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MP0 Y A VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MN0 Y A VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_4_iso A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MP0 Y A VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MN0 Y A VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_4_digisub A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MP0 Y A VDD VDD sg13_lv_pmos m=4 w=1.12u l=130.00n ng=1
+MN0 Y A VSS VSS sg13_lv_nmos m=4 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/layout/sg13g2_inv_8.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/layout/sg13g2_inv_8.gds
new file mode 100644
index 00000000..7eaec21c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/layout/sg13g2_inv_8.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/netlist/sg13g2_inv_8.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/netlist/sg13g2_inv_8.cdl
new file mode 100644
index 00000000..fa7f447e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_inv_8/netlist/sg13g2_inv_8.cdl
@@ -0,0 +1,43 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_inv_8
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_inv_8 A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_8_iso A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_inv_8_digisub A VDD VSS Y
+*.PININFO A:I Y:O VDD:B VSS:B
+MX1 Y A VSS VSS sg13_lv_nmos m=8 w=740.00n l=130.00n ng=1
+MX0 Y A VDD VDD sg13_lv_pmos m=8 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/layout/sg13g2_lgcp_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/layout/sg13g2_lgcp_1.gds
new file mode 100644
index 00000000..8458b07e
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/layout/sg13g2_lgcp_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/netlist/sg13g2_lgcp_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/netlist/sg13g2_lgcp_1.cdl
new file mode 100644
index 00000000..a73c4486
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_lgcp_1/netlist/sg13g2_lgcp_1.cdl
@@ -0,0 +1,100 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_lgcp_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_lgcp_1 CLK GATE GCLK VDD VSS
+*.PININFO CLK:I GATE:I GCLK:O VDD:B VSS:B
+MX15 CLKBB CLKB VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_83_260_ CLKBB a_258_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX12 int_GATE a_83_260_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX11 a_258_392_ GATE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX9 a_987_393_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 GCLK a_987_393_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 a_83_260_ CLKB a_484_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX4 CLKB CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_987_393_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_484_508_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX19 GCLK a_987_393_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_987_393_ int_GATE a_984_125_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX17 int_GATE a_83_260_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 CLKBB CLKB VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 a_477_124_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_267_80_ GATE VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 a_83_260_ CLKBB a_477_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX6 CLKB CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 a_984_125_ CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_83_260_ CLKB a_267_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_lgcp_1_iso CLK GATE GCLK VDD VSS
+*.PININFO CLK:I GATE:I GCLK:O VDD:B VSS:B
+MX15 CLKBB CLKB VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_83_260_ CLKBB a_258_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX12 int_GATE a_83_260_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX11 a_258_392_ GATE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX9 a_987_393_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 GCLK a_987_393_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 a_83_260_ CLKB a_484_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX4 CLKB CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_987_393_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_484_508_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX19 GCLK a_987_393_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_987_393_ int_GATE a_984_125_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX17 int_GATE a_83_260_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 CLKBB CLKB VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 a_477_124_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_267_80_ GATE VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 a_83_260_ CLKBB a_477_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX6 CLKB CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 a_984_125_ CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_83_260_ CLKB a_267_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_lgcp_1_digisub CLK GATE GCLK VDD VSS
+*.PININFO CLK:I GATE:I GCLK:O VDD:B VSS:B
+MX15 CLKBB CLKB VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_83_260_ CLKBB a_258_392_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX12 int_GATE a_83_260_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX11 a_258_392_ GATE VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX9 a_987_393_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 GCLK a_987_393_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 a_83_260_ CLKB a_484_508_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX4 CLKB CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_987_393_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX2 a_484_508_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX19 GCLK a_987_393_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 a_987_393_ int_GATE a_984_125_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX17 int_GATE a_83_260_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX16 CLKBB CLKB VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX13 a_477_124_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_267_80_ GATE VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 a_83_260_ CLKBB a_477_124_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX6 CLKB CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 a_984_125_ CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 a_83_260_ CLKB a_267_80_ VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/layout/sg13g2_mux2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/layout/sg13g2_mux2_1.gds
new file mode 100644
index 00000000..1d24518d
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/layout/sg13g2_mux2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/netlist/sg13g2_mux2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/netlist/sg13g2_mux2_1.cdl
new file mode 100644
index 00000000..2bfe2c88
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_1/netlist/sg13g2_mux2_1.cdl
@@ -0,0 +1,73 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_mux2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_mux2_1 A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux2_1_iso A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux2_1_digisub A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/layout/sg13g2_mux2_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/layout/sg13g2_mux2_2.gds
new file mode 100644
index 00000000..85ea9e52
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/layout/sg13g2_mux2_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/netlist/sg13g2_mux2_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/netlist/sg13g2_mux2_2.cdl
new file mode 100644
index 00000000..b281c240
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux2_2/netlist/sg13g2_mux2_2.cdl
@@ -0,0 +1,73 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_mux2_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_mux2_2 A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux2_2_iso A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux2_2_digisub A0 A1 S VDD VSS X
+*.PININFO A0:I A1:I S:I X:O VDD:B VSS:B
+MP0 net4 S VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP4 X net6 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP3 net6 A1 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP5 Sb S VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 net5 Sb VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net6 A0 net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MN4 net3 S VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN1 net1 Sb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 X net6 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN5 Sb S VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net6 A1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net6 A0 net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/layout/sg13g2_mux4_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/layout/sg13g2_mux4_1.gds
new file mode 100644
index 00000000..81d93d7f
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/layout/sg13g2_mux4_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/netlist/sg13g2_mux4_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/netlist/sg13g2_mux4_1.cdl
new file mode 100644
index 00000000..4fce33bf
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_mux4_1/netlist/sg13g2_mux4_1.cdl
@@ -0,0 +1,115 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_mux4_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_mux4_1 A0 A1 A2 A3 S0 S1 VDD VSS X
+*.PININFO A0:I A1:I A2:I A3:I S0:I S1:I X:O VDD:B VSS:B
+MN12 X Xb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN18 low S0b net7 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN17 net7 A0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN19 low S1b Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN10 high S1 Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN9 net4 A3 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN8 high S0 net4 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN14 net6 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN13 high S0b net6 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN16 net2 A1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN15 low S0 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 S1b S1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 S0b S0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP19 low S1 Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 high S1b Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP10 X Xb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP9 high S0b net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP8 net3 A3 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP14 high S0 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP13 net5 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP18 net8 A0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP17 low S0 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 S1b S1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 S0b S0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP16 low S0b net1 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP15 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux4_1_iso A0 A1 A2 A3 S0 S1 VDD VSS X
+*.PININFO A0:I A1:I A2:I A3:I S0:I S1:I X:O VDD:B VSS:B
+MN12 X Xb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN18 low S0b net7 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN17 net7 A0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN19 low S1b Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN10 high S1 Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN9 net4 A3 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN8 high S0 net4 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN14 net6 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN13 high S0b net6 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN16 net2 A1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN15 low S0 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 S1b S1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 S0b S0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP19 low S1 Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 high S1b Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP10 X Xb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP9 high S0b net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP8 net3 A3 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP14 high S0 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP13 net5 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP18 net8 A0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP17 low S0 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 S1b S1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 S0b S0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP16 low S0b net1 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP15 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_mux4_1_digisub A0 A1 A2 A3 S0 S1 VDD VSS X
+*.PININFO A0:I A1:I A2:I A3:I S0:I S1:I X:O VDD:B VSS:B
+MN12 X Xb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN18 low S0b net7 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN17 net7 A0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN19 low S1b Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN10 high S1 Xb VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN9 net4 A3 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN8 high S0 net4 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN14 net6 A2 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN13 high S0b net6 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN16 net2 A1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN15 low S0 net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN1 S1b S1 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN0 S0b S0 VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MP19 low S1 Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP11 high S1b Xb VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP10 X Xb VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP9 high S0b net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP8 net3 A3 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP14 high S0 net5 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP13 net5 A2 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP18 net8 A0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP17 low S0 net8 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 S1b S1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 S0b S0 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP16 low S0b net1 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP15 net1 A1 VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/layout/sg13g2_nand2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/layout/sg13g2_nand2_1.gds
new file mode 100644
index 00000000..b90666fc
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/layout/sg13g2_nand2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/netlist/sg13g2_nand2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/netlist/sg13g2_nand2_1.cdl
new file mode 100644
index 00000000..94137096
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_1/netlist/sg13g2_nand2_1.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand2_1 A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2_1_iso A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2_1_digisub A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/layout/sg13g2_nand2_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/layout/sg13g2_nand2_2.gds
new file mode 100644
index 00000000..b258553b
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/layout/sg13g2_nand2_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/netlist/sg13g2_nand2_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/netlist/sg13g2_nand2_2.cdl
new file mode 100644
index 00000000..4aca1caa
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2_2/netlist/sg13g2_nand2_2.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand2_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand2_2 A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2_2_iso A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2_2_digisub A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP1 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MP0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MN0 Y A net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/layout/sg13g2_nand2b_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/layout/sg13g2_nand2b_1.gds
new file mode 100644
index 00000000..c4697389
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/layout/sg13g2_nand2b_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/netlist/sg13g2_nand2b_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/netlist/sg13g2_nand2b_1.cdl
new file mode 100644
index 00000000..8ac4e864
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_1/netlist/sg13g2_nand2b_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand2b_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand2b_1 A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y a_27_112_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 a_27_112_ A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y a_27_112_ net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_27_112_ A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2b_1_iso A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y a_27_112_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 a_27_112_ A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y a_27_112_ net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_27_112_ A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2b_1_digisub A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y a_27_112_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 a_27_112_ A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y a_27_112_ net1 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_27_112_ A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/layout/sg13g2_nand2b_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/layout/sg13g2_nand2b_2.gds
new file mode 100644
index 00000000..b731a818
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/layout/sg13g2_nand2b_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/netlist/sg13g2_nand2b_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/netlist/sg13g2_nand2b_2.cdl
new file mode 100644
index 00000000..f7276c37
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand2b_2/netlist/sg13g2_nand2b_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand2b_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand2b_2 A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 A A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y B net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX4 A A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2b_2_iso A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 A A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y B net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX4 A A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand2b_2_digisub A_N B VDD VSS Y
+*.PININFO A_N:I B:I Y:O VDD:B VSS:B
+MX0 Y A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 A A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 Y B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y B net1 VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX4 A A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX5 net1 A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/layout/sg13g2_nand3_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/layout/sg13g2_nand3_1.gds
new file mode 100644
index 00000000..dd2a9d4a
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/layout/sg13g2_nand3_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/netlist/sg13g2_nand3_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/netlist/sg13g2_nand3_1.cdl
new file mode 100644
index 00000000..69709bce
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3_1/netlist/sg13g2_nand3_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand3_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand3_1 A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand3_1_iso A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand3_1_digisub A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/layout/sg13g2_nand3b_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/layout/sg13g2_nand3b_1.gds
new file mode 100644
index 00000000..36d6a4db
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/layout/sg13g2_nand3b_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/netlist/sg13g2_nand3b_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/netlist/sg13g2_nand3b_1.cdl
new file mode 100644
index 00000000..59204ca6
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand3b_1/netlist/sg13g2_nand3b_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand3b_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand3b_1 A_N B C VDD VSS Y
+*.PININFO A_N:I B:I C:I Y:O VDD:B VSS:B
+MX0 net1 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net1 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand3b_1_iso A_N B C VDD VSS Y
+*.PININFO A_N:I B:I C:I Y:O VDD:B VSS:B
+MX0 net1 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net1 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand3b_1_digisub A_N B C VDD VSS Y
+*.PININFO A_N:I B:I C:I Y:O VDD:B VSS:B
+MX0 net1 A_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX5 net1 A_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 Y net1 net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/layout/sg13g2_nand4_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/layout/sg13g2_nand4_1.gds
new file mode 100644
index 00000000..45edea39
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/layout/sg13g2_nand4_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/netlist/sg13g2_nand4_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/netlist/sg13g2_nand4_1.cdl
new file mode 100644
index 00000000..3a0039e9
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nand4_1/netlist/sg13g2_nand4_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nand4_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nand4_1 A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MP0 Y D VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand4_1_iso A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MP0 Y D VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nand4_1_digisub A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MP0 Y D VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 Y C VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net2 B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 net3 C net5 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX7 Y A net2 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN0 net5 D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/layout/sg13g2_nor2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/layout/sg13g2_nor2_1.gds
new file mode 100644
index 00000000..236acc49
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/layout/sg13g2_nor2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/netlist/sg13g2_nor2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/netlist/sg13g2_nor2_1.cdl
new file mode 100644
index 00000000..d6da0c37
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_1/netlist/sg13g2_nor2_1.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor2_1 A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2_1_iso A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2_1_digisub A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/layout/sg13g2_nor2_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/layout/sg13g2_nor2_2.gds
new file mode 100644
index 00000000..cb1f5bbb
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/layout/sg13g2_nor2_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/netlist/sg13g2_nor2_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/netlist/sg13g2_nor2_2.cdl
new file mode 100644
index 00000000..6d64ac7b
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2_2/netlist/sg13g2_nor2_2.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor2_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor2_2 A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+.ENDS
+
+.SUBCKT sg13g2_nor2_2_iso A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+.ENDS
+
+.SUBCKT sg13g2_nor2_2_digisub A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=1.48u l=130.00n ng=2
+MX1 net1 A VDD VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+MX2 Y B net1 VDD sg13_lv_pmos m=1 w=2.24u l=130.00n ng=2
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/layout/sg13g2_nor2b_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/layout/sg13g2_nor2b_1.gds
new file mode 100644
index 00000000..f26fa425
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/layout/sg13g2_nor2b_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/netlist/sg13g2_nor2b_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/netlist/sg13g2_nor2b_1.cdl
new file mode 100644
index 00000000..b2ada9e4
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_1/netlist/sg13g2_nor2b_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor2b_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor2b_1 A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2b_1_iso A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2b_1_digisub A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/layout/sg13g2_nor2b_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/layout/sg13g2_nor2b_2.gds
new file mode 100644
index 00000000..e2be8c6c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/layout/sg13g2_nor2b_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/netlist/sg13g2_nor2b_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/netlist/sg13g2_nor2b_2.cdl
new file mode 100644
index 00000000..cb572b24
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor2b_2/netlist/sg13g2_nor2b_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor2b_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor2b_2 A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2b_2_iso A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor2b_2_digisub A B_N VDD VSS Y
+*.PININFO A:I B_N:I Y:O VDD:B VSS:B
+MN0 B B_N VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX0 Y A VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=720.00n l=130.00n ng=1
+MP0 B B_N VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX1 net1 B VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 Y A net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/layout/sg13g2_nor3_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/layout/sg13g2_nor3_1.gds
new file mode 100644
index 00000000..c18b5baf
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/layout/sg13g2_nor3_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/netlist/sg13g2_nor3_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/netlist/sg13g2_nor3_1.cdl
new file mode 100644
index 00000000..a43ce03c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_1/netlist/sg13g2_nor3_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor3_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor3_1 A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor3_1_iso A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor3_1_digisub A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=1 w=770.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/layout/sg13g2_nor3_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/layout/sg13g2_nor3_2.gds
new file mode 100644
index 00000000..6a66fa13
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/layout/sg13g2_nor3_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/netlist/sg13g2_nor3_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/netlist/sg13g2_nor3_2.cdl
new file mode 100644
index 00000000..c4e8658e
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor3_2/netlist/sg13g2_nor3_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor3_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor3_2 A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor3_2_iso A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor3_2_digisub A B C VDD VSS Y
+*.PININFO A:I B:I C:I Y:O VDD:B VSS:B
+MX3 net1 C Y VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX0 net2 B net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX2 VDD A net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX4 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX1 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX5 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/layout/sg13g2_nor4_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/layout/sg13g2_nor4_1.gds
new file mode 100644
index 00000000..57646f86
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/layout/sg13g2_nor4_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/netlist/sg13g2_nor4_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/netlist/sg13g2_nor4_1.cdl
new file mode 100644
index 00000000..c28c9fdb
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_1/netlist/sg13g2_nor4_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor4_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor4_1 A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor4_1_iso A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor4_1_digisub A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/layout/sg13g2_nor4_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/layout/sg13g2_nor4_2.gds
new file mode 100644
index 00000000..8ec2c201
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/layout/sg13g2_nor4_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/netlist/sg13g2_nor4_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/netlist/sg13g2_nor4_2.cdl
new file mode 100644
index 00000000..f2a0d2de
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_nor4_2/netlist/sg13g2_nor4_2.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_nor4_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_nor4_2 A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor4_2_iso A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_nor4_2_digisub A B C D VDD VSS Y
+*.PININFO A:I B:I C:I D:I Y:O VDD:B VSS:B
+MX0 net3 A VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX5 net2 B net3 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX6 net1 C net2 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX7 Y D net1 VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX1 Y A VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX2 Y D VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX3 Y B VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX4 Y C VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/layout/sg13g2_o21ai_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/layout/sg13g2_o21ai_1.gds
new file mode 100644
index 00000000..26e7779c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/layout/sg13g2_o21ai_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/netlist/sg13g2_o21ai_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/netlist/sg13g2_o21ai_1.cdl
new file mode 100644
index 00000000..1ed19210
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_o21ai_1/netlist/sg13g2_o21ai_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_o21ai_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_o21ai_1 A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MP2 net14 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP1 Y A2 net14 VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP0 Y B1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MN2 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN3 net1 A1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_o21ai_1_iso A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MP2 net14 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP1 Y A2 net14 VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP0 Y B1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MN2 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN3 net1 A1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_o21ai_1_digisub A1 A2 B1 VDD VSS Y
+*.PININFO A1:I A2:I B1:I Y:O VDD:B VSS:B
+MP2 net14 A1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP1 Y A2 net14 VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MP0 Y B1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=150.00n ng=1
+MN2 net1 A2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN3 net1 A1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+MN0 Y B1 net1 VSS sg13_lv_nmos m=1 w=740.00n l=150.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/layout/sg13g2_or2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/layout/sg13g2_or2_1.gds
new file mode 100644
index 00000000..23e35b11
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/layout/sg13g2_or2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/netlist/sg13g2_or2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/netlist/sg13g2_or2_1.cdl
new file mode 100644
index 00000000..bb88192c
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_1/netlist/sg13g2_or2_1.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or2_1 A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or2_1_iso A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or2_1_digisub A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/layout/sg13g2_or2_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/layout/sg13g2_or2_2.gds
new file mode 100644
index 00000000..0ab79d0a
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/layout/sg13g2_or2_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/netlist/sg13g2_or2_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/netlist/sg13g2_or2_2.cdl
new file mode 100644
index 00000000..d9eb4679
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or2_2/netlist/sg13g2_or2_2.cdl
@@ -0,0 +1,55 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or2_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or2_2 A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or2_2_iso A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or2_2_digisub A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MP0 net2 B net3 VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP1 net3 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP2 X net2 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MN0 net2 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net2 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 X net2 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/layout/sg13g2_or3_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/layout/sg13g2_or3_1.gds
new file mode 100644
index 00000000..eb76d595
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/layout/sg13g2_or3_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/netlist/sg13g2_or3_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/netlist/sg13g2_or3_1.cdl
new file mode 100644
index 00000000..648e81ea
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_1/netlist/sg13g2_or3_1.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or3_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or3_1 A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or3_1_iso A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or3_1_digisub A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/layout/sg13g2_or3_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/layout/sg13g2_or3_2.gds
new file mode 100644
index 00000000..1bafd94f
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/layout/sg13g2_or3_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/netlist/sg13g2_or3_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/netlist/sg13g2_or3_2.cdl
new file mode 100644
index 00000000..24142f8b
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or3_2/netlist/sg13g2_or3_2.cdl
@@ -0,0 +1,61 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or3_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or3_2 A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or3_2_iso A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or3_2_digisub A B C VDD VSS X
+*.PININFO A:I B:I C:I X:O VDD:B VSS:B
+MX0 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MX6 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX7 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX2 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+MX3 net9 B net12 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX4 net12 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX5 net1 C net9 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/layout/sg13g2_or4_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/layout/sg13g2_or4_1.gds
new file mode 100644
index 00000000..4eafb789
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/layout/sg13g2_or4_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/netlist/sg13g2_or4_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/netlist/sg13g2_or4_1.cdl
new file mode 100644
index 00000000..c590e5e0
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_1/netlist/sg13g2_or4_1.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or4_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or4_1 A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or4_1_iso A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or4_1_digisub A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/layout/sg13g2_or4_2.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/layout/sg13g2_or4_2.gds
new file mode 100644
index 00000000..628521e0
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/layout/sg13g2_or4_2.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/netlist/sg13g2_or4_2.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/netlist/sg13g2_or4_2.cdl
new file mode 100644
index 00000000..c2ebf8b4
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_or4_2/netlist/sg13g2_or4_2.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_or4_2
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_or4_2 A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or4_2_iso A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_or4_2_digisub A B C D VDD VSS X
+*.PININFO A:I B:I C:I D:I X:O VDD:B VSS:B
+MN4 X net1 VSS VSS sg13_lv_nmos m=2 w=740.00n l=130.00n ng=1
+MN3 net1 D VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN2 net1 C VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN1 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MN0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MP4 net4 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP3 net3 B net4 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP2 net2 C net3 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP1 net1 D net2 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MP0 X net1 VDD VDD sg13_lv_pmos m=2 w=1.12u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/layout/sg13g2_sdfbbp_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/layout/sg13g2_sdfbbp_1.gds
new file mode 100644
index 00000000..c54f3d45
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/layout/sg13g2_sdfbbp_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/netlist/sg13g2_sdfbbp_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/netlist/sg13g2_sdfbbp_1.cdl
new file mode 100644
index 00000000..c4dc5820
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sdfbbp_1/netlist/sg13g2_sdfbbp_1.cdl
@@ -0,0 +1,226 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_sdfbbp_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_sdfbbp_1 CLK D Q Q_N RESET_B SCD SCE SET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I SET_B:I Q:O Q_N:O VDD:B VSS:B
+MX46 a_1625_93_ RESET_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX45 a_2037_442_ a_1878_420_ a_2384_392_ VDD sg13_lv_pmos m=1 w=1.000u 
++ l=130.00n ng=1
+MX44 VDD SET_B a_2037_442_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX41 VDD a_622_98_ a_877_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX39 VDD SCE a_341_93_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX38 a_218_464_ D a_197_119_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX33 a_1092_96_ a_622_98_ a_1221_419_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX28 a_1221_419_ a_1250_231_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX27 VDD SCE a_218_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX26 VDD a_2037_442_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX24 VDD a_1250_231_ a_1766_379_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX19 a_2384_392_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD SET_B a_1250_231_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 a_27_464_ SCD VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX15 a_622_98_ CLK VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX14 a_1250_231_ a_1092_96_ a_1580_379_ VDD sg13_lv_pmos m=1 w=840.00n 
++ l=130.00n ng=1
+MX11 a_197_119_ a_877_98_ a_1092_96_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_197_119_ a_341_93_ a_27_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX8 a_2881_74_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 a_1580_379_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1986_504_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_1878_420_ a_877_98_ a_1986_504_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 a_1766_379_ a_622_98_ a_1878_420_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n 
++ ng=1
+MX3 VDD a_2881_74_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX47 a_2271_74_ a_1878_420_ a_2037_442_ VSS sg13_lv_nmos m=1 w=740.00n 
++ l=130.00n ng=1
+MX43 a_197_119_ a_622_98_ a_1092_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX42 a_299_119_ a_341_93_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX40 VSS a_622_98_ a_877_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX37 a_1625_93_ RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX36 a_2061_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX35 a_1418_125_ a_1092_96_ a_1250_231_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX34 VSS SCE a_341_93_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX32 VSS SET_B a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX31 a_1192_96_ a_1250_231_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX30 a_119_119_ SCE a_197_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX29 VSS SET_B a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX25 a_1092_96_ a_877_98_ a_1192_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX23 a_197_119_ D a_299_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX22 a_2881_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX21 a_1878_420_ a_622_98_ a_2061_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX20 VSS a_2881_74_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VSS a_1250_231_ a_1880_119_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX13 a_622_98_ CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX12 VSS SCD a_119_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1880_119_ a_877_98_ a_1878_420_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX2 a_1250_231_ a_1625_93_ a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX1 VSS a_2037_442_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_2037_442_ a_1625_93_ a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+.ENDS
+
+.SUBCKT sg13g2_sdfbbp_1_iso CLK D Q Q_N RESET_B SCD SCE SET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I SET_B:I Q:O Q_N:O VDD:B VSS:B
+MX46 a_1625_93_ RESET_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX45 a_2037_442_ a_1878_420_ a_2384_392_ VDD sg13_lv_pmos m=1 w=1.000u 
++ l=130.00n ng=1
+MX44 VDD SET_B a_2037_442_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX41 VDD a_622_98_ a_877_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX39 VDD SCE a_341_93_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX38 a_218_464_ D a_197_119_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX33 a_1092_96_ a_622_98_ a_1221_419_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX28 a_1221_419_ a_1250_231_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX27 VDD SCE a_218_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX26 VDD a_2037_442_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX24 VDD a_1250_231_ a_1766_379_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX19 a_2384_392_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD SET_B a_1250_231_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 a_27_464_ SCD VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX15 a_622_98_ CLK VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX14 a_1250_231_ a_1092_96_ a_1580_379_ VDD sg13_lv_pmos m=1 w=840.00n 
++ l=130.00n ng=1
+MX11 a_197_119_ a_877_98_ a_1092_96_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_197_119_ a_341_93_ a_27_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX8 a_2881_74_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 a_1580_379_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1986_504_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_1878_420_ a_877_98_ a_1986_504_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 a_1766_379_ a_622_98_ a_1878_420_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n 
++ ng=1
+MX3 VDD a_2881_74_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX47 a_2271_74_ a_1878_420_ a_2037_442_ VSS sg13_lv_nmos m=1 w=740.00n 
++ l=130.00n ng=1
+MX43 a_197_119_ a_622_98_ a_1092_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX42 a_299_119_ a_341_93_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX40 VSS a_622_98_ a_877_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX37 a_1625_93_ RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX36 a_2061_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX35 a_1418_125_ a_1092_96_ a_1250_231_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX34 VSS SCE a_341_93_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX32 VSS SET_B a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX31 a_1192_96_ a_1250_231_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX30 a_119_119_ SCE a_197_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX29 VSS SET_B a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX25 a_1092_96_ a_877_98_ a_1192_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX23 a_197_119_ D a_299_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX22 a_2881_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX21 a_1878_420_ a_622_98_ a_2061_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX20 VSS a_2881_74_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VSS a_1250_231_ a_1880_119_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX13 a_622_98_ CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX12 VSS SCD a_119_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1880_119_ a_877_98_ a_1878_420_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX2 a_1250_231_ a_1625_93_ a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX1 VSS a_2037_442_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_2037_442_ a_1625_93_ a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+.ENDS
+
+.SUBCKT sg13g2_sdfbbp_1_digisub CLK D Q Q_N RESET_B SCD SCE SET_B VDD VSS
+*.PININFO CLK:I D:I RESET_B:I SCD:I SCE:I SET_B:I Q:O Q_N:O VDD:B VSS:B
+MX46 a_1625_93_ RESET_B VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX45 a_2037_442_ a_1878_420_ a_2384_392_ VDD sg13_lv_pmos m=1 w=1.000u 
++ l=130.00n ng=1
+MX44 VDD SET_B a_2037_442_ VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX41 VDD a_622_98_ a_877_98_ VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX39 VDD SCE a_341_93_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX38 a_218_464_ D a_197_119_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX33 a_1092_96_ a_622_98_ a_1221_419_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX28 a_1221_419_ a_1250_231_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX27 VDD SCE a_218_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX26 VDD a_2037_442_ Q_N VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX24 VDD a_1250_231_ a_1766_379_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX19 a_2384_392_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX17 VDD SET_B a_1250_231_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 a_27_464_ SCD VDD VDD sg13_lv_pmos m=1 w=640.00n l=130.00n ng=1
+MX15 a_622_98_ CLK VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX14 a_1250_231_ a_1092_96_ a_1580_379_ VDD sg13_lv_pmos m=1 w=840.00n 
++ l=130.00n ng=1
+MX11 a_197_119_ a_877_98_ a_1092_96_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX9 a_197_119_ a_341_93_ a_27_464_ VDD sg13_lv_pmos m=1 w=640.00n l=130.00n 
++ ng=1
+MX8 a_2881_74_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX7 a_1580_379_ a_1625_93_ VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX6 a_1986_504_ a_2037_442_ VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX5 a_1878_420_ a_877_98_ a_1986_504_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX4 a_1766_379_ a_622_98_ a_1878_420_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n 
++ ng=1
+MX3 VDD a_2881_74_ Q VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX47 a_2271_74_ a_1878_420_ a_2037_442_ VSS sg13_lv_nmos m=1 w=740.00n 
++ l=130.00n ng=1
+MX43 a_197_119_ a_622_98_ a_1092_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX42 a_299_119_ a_341_93_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX40 VSS a_622_98_ a_877_98_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX37 a_1625_93_ RESET_B VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX36 a_2061_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX35 a_1418_125_ a_1092_96_ a_1250_231_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX34 VSS SCE a_341_93_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX32 VSS SET_B a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX31 a_1192_96_ a_1250_231_ VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX30 a_119_119_ SCE a_197_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX29 VSS SET_B a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX25 a_1092_96_ a_877_98_ a_1192_96_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX23 a_197_119_ D a_299_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX22 a_2881_74_ a_2037_442_ VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX21 a_1878_420_ a_622_98_ a_2061_74_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n 
++ ng=1
+MX20 VSS a_2881_74_ Q VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX18 VSS a_1250_231_ a_1880_119_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX13 a_622_98_ CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX12 VSS SCD a_119_119_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1880_119_ a_877_98_ a_1878_420_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX2 a_1250_231_ a_1625_93_ a_1418_125_ VSS sg13_lv_nmos m=1 w=550.00n 
++ l=130.00n ng=1
+MX1 VSS a_2037_442_ Q_N VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_2037_442_ a_1625_93_ a_2271_74_ VSS sg13_lv_nmos m=1 w=740.00n l=130.00n 
++ ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/layout/sg13g2_sighold.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/layout/sg13g2_sighold.gds
new file mode 100644
index 00000000..14de95c2
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/layout/sg13g2_sighold.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/netlist/sg13g2_sighold.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/netlist/sg13g2_sighold.cdl
new file mode 100644
index 00000000..fd285100
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_sighold/netlist/sg13g2_sighold.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_sighold
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_sighold SH VDD VSS
+*.PININFO SH:B VDD:B VSS:B
+MN0 net1 SH VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1
+MN1 SH net1 VSS VSS sg13_lv_nmos m=1 w=300.0n l=700.0n ng=1
+MP0 net1 SH VDD VDD sg13_lv_pmos m=1 w=450.00n l=130.00n ng=1
+MP1 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1
+.ENDS
+
+.SUBCKT sg13g2_sighold_iso SH VDD VSS
+*.PININFO SH:B VDD:B VSS:B
+MN0 net1 SH VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1
+MN1 SH net1 VSS VSS sg13_lv_nmos m=1 w=300.0n l=700.0n ng=1
+MP0 net1 SH VDD VDD sg13_lv_pmos m=1 w=450.00n l=130.00n ng=1
+MP1 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1
+.ENDS
+
+.SUBCKT sg13g2_sighold_digisub SH VDD VSS
+*.PININFO SH:B VDD:B VSS:B
+MN0 net1 SH VSS VSS sg13_lv_nmos m=1 w=300.0n l=130.00n ng=1
+MN1 SH net1 VSS VSS sg13_lv_nmos m=1 w=300.0n l=700.0n ng=1
+MP0 net1 SH VDD VDD sg13_lv_pmos m=1 w=450.00n l=130.00n ng=1
+MP1 SH net1 VDD VDD sg13_lv_pmos m=1 w=300.0n l=700.0n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/layout/sg13g2_slgcp_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/layout/sg13g2_slgcp_1.gds
new file mode 100644
index 00000000..19cca9e7
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/layout/sg13g2_slgcp_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/netlist/sg13g2_slgcp_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/netlist/sg13g2_slgcp_1.cdl
new file mode 100644
index 00000000..21b58d98
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_slgcp_1/netlist/sg13g2_slgcp_1.cdl
@@ -0,0 +1,103 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_slgcp_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_slgcp_1 CLK GATE GCLK SCE VDD VSS
+*.PININFO CLK:I GATE:I SCE:I GCLK:O VDD:B VSS:B
+MX19 GCLK a_1238_94_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX18 a_114_112_ CLKbb a_566_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_1238_94_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_116_424_ SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 a_566_74_ CLKb a_722_492_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 int_GATE a_566_74_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_1238_94_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_722_492_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX2 a_114_112_ GATE a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX21 int_GATE a_566_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX20 net2 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX17 a_114_112_ SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_566_74_ CLKb a_114_112_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX12 a_667_80_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1238_94_ int_GATE net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 GCLK a_1238_94_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_114_112_ GATE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_566_74_ CLKbb a_667_80_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_slgcp_1_iso CLK GATE GCLK SCE VDD VSS
+*.PININFO CLK:I GATE:I SCE:I GCLK:O VDD:B VSS:B
+MX19 GCLK a_1238_94_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX18 a_114_112_ CLKbb a_566_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_1238_94_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_116_424_ SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 a_566_74_ CLKb a_722_492_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 int_GATE a_566_74_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_1238_94_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_722_492_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX2 a_114_112_ GATE a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX21 int_GATE a_566_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX20 net2 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX17 a_114_112_ SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_566_74_ CLKb a_114_112_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX12 a_667_80_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1238_94_ int_GATE net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 GCLK a_1238_94_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_114_112_ GATE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_566_74_ CLKbb a_667_80_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_slgcp_1_digisub CLK GATE GCLK SCE VDD VSS
+*.PININFO CLK:I GATE:I SCE:I GCLK:O VDD:B VSS:B
+MX19 GCLK a_1238_94_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX18 a_114_112_ CLKbb a_566_74_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX16 CLKbb CLKb VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX14 a_1238_94_ int_GATE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX13 a_116_424_ SCE VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX11 a_566_74_ CLKb a_722_492_ VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX9 int_GATE a_566_74_ VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 CLKb CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX5 a_1238_94_ CLK VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX3 a_722_492_ int_GATE VDD VDD sg13_lv_pmos m=1 w=420.00n l=130.00n ng=1
+MX2 a_114_112_ GATE a_116_424_ VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MX21 int_GATE a_566_74_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX20 net2 CLK VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX17 a_114_112_ SCE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX15 a_566_74_ CLKb a_114_112_ VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX12 a_667_80_ int_GATE VSS VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+MX10 a_1238_94_ int_GATE net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MX8 GCLK a_1238_94_ VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 CLKbb CLKb VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX4 a_114_112_ GATE VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 CLKb CLK VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX0 a_566_74_ CLKbb a_667_80_ VSS sg13_lv_nmos m=1 w=420.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/layout/sg13g2_tiehi.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/layout/sg13g2_tiehi.gds
new file mode 100644
index 00000000..22e34052
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/layout/sg13g2_tiehi.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/netlist/sg13g2_tiehi.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/netlist/sg13g2_tiehi.cdl
new file mode 100644
index 00000000..0963e286
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tiehi/netlist/sg13g2_tiehi.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_tiehi
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_tiehi L_HI VDD VSS
+*.PININFO L_HI:O VDD:B VSS:B
+MMN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=795.00n l=130.00n ng=1
+MMN1 net1 net1 VSS VSS sg13_lv_nmos m=1 w=300n l=130.00n ng=1
+MMP2 L_HI net3 VDD VDD sg13_lv_pmos m=1 w=1.155u l=130.00n ng=1
+MMP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_tiehi_iso L_HI VDD VSS
+*.PININFO L_HI:O VDD:B VSS:B
+MMN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=795.00n l=130.00n ng=1
+MMN1 net1 net1 VSS VSS sg13_lv_nmos m=1 w=300n l=130.00n ng=1
+MMP2 L_HI net3 VDD VDD sg13_lv_pmos m=1 w=1.155u l=130.00n ng=1
+MMP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_tiehi_digisub L_HI VDD VSS
+*.PININFO L_HI:O VDD:B VSS:B
+MMN2 net3 net2 VSS VSS sg13_lv_nmos m=1 w=795.00n l=130.00n ng=1
+MMN1 net1 net1 VSS VSS sg13_lv_nmos m=1 w=300n l=130.00n ng=1
+MMP2 L_HI net3 VDD VDD sg13_lv_pmos m=1 w=1.155u l=130.00n ng=1
+MMP1 net2 net1 VDD VDD sg13_lv_pmos m=1 w=660.0n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/layout/sg13g2_tielo.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/layout/sg13g2_tielo.gds
new file mode 100644
index 00000000..9ad646fa
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/layout/sg13g2_tielo.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/netlist/sg13g2_tielo.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/netlist/sg13g2_tielo.cdl
new file mode 100644
index 00000000..df8b4fa5
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_tielo/netlist/sg13g2_tielo.cdl
@@ -0,0 +1,49 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_tielo
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_tielo L_LO VDD VSS
+*.PININFO L_LO:O VDD:B VSS:B
+MMN1 net3 net2 VSS VSS sg13_lv_nmos m=1 w=385.00n l=130.00n ng=1
+MMN2 L_LO net1 VSS VSS sg13_lv_nmos m=1 w=880.0n l=130.00n ng=1
+MMP1 net2 net2 VDD VDD sg13_lv_pmos m=1 w=300n l=130.00n ng=1
+MMP2 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_tielo_iso L_LO VDD VSS
+*.PININFO L_LO:O VDD:B VSS:B
+MMN1 net3 net2 VSS VSS sg13_lv_nmos m=1 w=385.00n l=130.00n ng=1
+MMN2 L_LO net1 VSS VSS sg13_lv_nmos m=1 w=880.0n l=130.00n ng=1
+MMP1 net2 net2 VDD VDD sg13_lv_pmos m=1 w=300n l=130.00n ng=1
+MMP2 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_tielo_digisub L_LO VDD VSS
+*.PININFO L_LO:O VDD:B VSS:B
+MMN1 net3 net2 VSS VSS sg13_lv_nmos m=1 w=385.00n l=130.00n ng=1
+MMN2 L_LO net1 VSS VSS sg13_lv_nmos m=1 w=880.0n l=130.00n ng=1
+MMP1 net2 net2 VDD VDD sg13_lv_pmos m=1 w=300n l=130.00n ng=1
+MMP2 net1 net3 VDD VDD sg13_lv_pmos m=1 w=1.045u l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/layout/sg13g2_xnor2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/layout/sg13g2_xnor2_1.gds
new file mode 100644
index 00000000..6f3e0d1c
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/layout/sg13g2_xnor2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/netlist/sg13g2_xnor2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/netlist/sg13g2_xnor2_1.cdl
new file mode 100644
index 00000000..4dc176e6
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xnor2_1/netlist/sg13g2_xnor2_1.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_xnor2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_xnor2_1 A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP9 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP8 Y B net4 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 net4 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MN4 Y net1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 net2 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN5 net1 B net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net3 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_xnor2_1_iso A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP9 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP8 Y B net4 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 net4 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MN4 Y net1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 net2 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN5 net1 B net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net3 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_xnor2_1_digisub A B VDD VSS Y
+*.PININFO A:I B:I Y:O VDD:B VSS:B
+MP9 Y net1 VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP8 Y B net4 VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP7 net4 A VDD VDD sg13_lv_pmos m=1 w=1.12u l=130.00n ng=1
+MP1 net1 B VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MP0 net1 A VDD VDD sg13_lv_pmos m=1 w=840.00n l=130.00n ng=1
+MN4 Y net1 net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN6 net2 A VSS VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN5 net1 B net2 VSS sg13_lv_nmos m=1 w=640.00n l=130.00n ng=1
+MN3 net3 B VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MN2 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/layout/sg13g2_xor2_1.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/layout/sg13g2_xor2_1.gds
new file mode 100644
index 00000000..26cde4bb
Binary files /dev/null and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/layout/sg13g2_xor2_1.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/netlist/sg13g2_xor2_1.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/netlist/sg13g2_xor2_1.cdl
new file mode 100644
index 00000000..19cabf44
--- /dev/null
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/sg13g2_cells/sg13g2_xor2_1/netlist/sg13g2_xor2_1.cdl
@@ -0,0 +1,67 @@
+************************************************************************
+* 
+* Copyright 2024 IHP PDK Authors
+* 
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+* 
+*    https://www.apache.org/licenses/LICENSE-2.0
+* 
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+* 
+************************************************************************
+
+
+************************************************************************
+* Library Name: sg13g2_stdcell
+* Cell Name:    sg13g2_xor2_1
+* View Name:    schematic
+************************************************************************
+
+.SUBCKT sg13g2_xor2_1 A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX4 X B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX9 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 net6 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 net1 B net6 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 net5 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net5 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_xor2_1_iso A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX4 X B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX9 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 net6 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 net1 B net6 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 net5 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net5 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
+.SUBCKT sg13g2_xor2_1_digisub A B VDD VSS X
+*.PININFO A:I B:I X:O VDD:B VSS:B
+MX0 net1 A VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX4 X B net3 VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX6 X net1 VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX8 net3 A VSS VSS sg13_lv_nmos m=1 w=740.00n l=130.00n ng=1
+MX9 net1 B VSS VSS sg13_lv_nmos m=1 w=550.00n l=130.00n ng=1
+MX1 net6 A VDD VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX2 net1 B net6 VDD sg13_lv_pmos m=1 w=1.000u l=130.00n ng=1
+MX3 net5 A VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX5 net5 B VDD VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+MX7 X net1 net5 VDD sg13_lv_pmos m=1 w=1.12e-06 l=130.00n ng=1
+.ENDS
+
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/cap_devices/netlist/cap_cmim.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/cap_devices/netlist/cap_cmim.cdl
index 5e06d42c..03c4f355 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/cap_devices/netlist/cap_cmim.cdl
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/cap_devices/netlist/cap_cmim.cdl
@@ -16,7 +16,7 @@
 *==========================================================================
 
 .SUBCKT cap_cmim
-C0 PLUS1 MINUS1 cap_cmim w=6.99u l=6.99u m=1
+C0 PLUS1 MINUS1 $[cap_cmim] 74.620f w=6.99u l=6.99u m=1
 C1 PLUS2 MINUS2 cap_cmim w=6.99u l=6.99u m=2
 C2 PLUS3 MINUS3 cap_cmim w=6.99u l=6.99u m=3
 
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rhigh.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rhigh.gds
index 8e6cb6f8..caa506de 100644
Binary files a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rhigh.gds and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rhigh.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rppd.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rppd.gds
index ebd40b4c..805db8de 100644
Binary files a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rppd.gds and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rppd.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rsil.gds b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rsil.gds
index ad0b758c..cc12cf0f 100644
Binary files a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rsil.gds and b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/layout/rsil.gds differ
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/lvsres.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/lvsres.cdl
index 4a00ea96..93fdf65b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/lvsres.cdl
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/lvsres.cdl
@@ -16,7 +16,7 @@
 *==========================================================================
 
 .SUBCKT lvsres
-Rm1 net1 net2 lvsres l=1u w=5u
-Rm2 net3 net4 lvsres l=1.5u w=5u
-Rm3 net5 net6 lvsres length=1u width=6u
+Rm1 net1 net2 $[lvsres] 20k l=1u w=5u
+Rm2 net3 net4 lvsres \ l=1.5u w =5u
+Rm3 net5 net6 lvsres / length =1u width=6u
 .ENDS
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rhigh.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rhigh.cdl
index 8c26874d..089192de 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rhigh.cdl
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rhigh.cdl
@@ -31,4 +31,85 @@ R3 p3 p4 rhigh w=0.5e-6 l=40e-6 m=1 b=0
 R1 p5 p_intern rhigh w=0.5e-6 l=30e-6 m=1 b=0
 R2 p_intern p6 rhigh w=0.5e-6 l=10e-6 m=1 b=0
 M1 p_intern G S B sg13_lv_nmos w=0.15e-6 l=0.2e-6 m=1 ng=1
+
+* Extra patterns
+R_pattern_1  a_1  b_1  rhigh w=5.85u l=5.4u b=3 ps=0.2u 
+R_pattern_2  a_2  b_2  rhigh w=1.67u l=9.14u b=6 ps=0.19u 
+R_pattern_3  a_3  b_3  rhigh w=4.69u l=7.11u b=4 ps=0.19u 
+R_pattern_4  a_4  b_4  rhigh w=5.02u l=0.82u b=4 ps=0.2u 
+R_pattern_5  a_5  b_5  rhigh w=0.64u l=6.3u b=2 ps=0.2u 
+R_pattern_6  a_6  b_6  rhigh w=4.64u l=1.98u b=4 ps=0.19u 
+R_pattern_7  a_7  b_7  rhigh w=3.93u l=9.34u b=8 ps=0.19u 
+R_pattern_8  a_8  b_8  rhigh w=5.1u l=3.03u b=9 ps=0.2u 
+R_pattern_9  a_9  b_9  rhigh w=5.1u l=9.34u b=4 ps=0.2u 
+R_pattern_10 a_10 b_10 rhigh w=3.93u l=1.98u b=2 ps=0.2u 
+R_pattern_11 a_11 b_11 rhigh w=4.64u l=6.3u b=4 ps=0.19u 
+R_pattern_12 a_12 b_12 rhigh w=0.64u l=0.82u b=4 ps=0.19u 
+R_pattern_13 a_13 b_13 rhigh w=5.02u l=7.11u b=6 ps=0.2u 
+R_pattern_14 a_14 b_14 rhigh w=4.69u l=9.14u b=3 ps=0.2u 
+R_pattern_15 a_15 b_15 rhigh w=1.67u l=5.4u b=9 ps=0.19u 
+R_pattern_16 a_16 b_16 rhigh w=5.85u l=3.03u b=8 ps=0.19u 
+R_pattern_17 a_17 b_17 rhigh w=1.67u l=3.03u b=2 ps=0.19u 
+R_pattern_18 a_18 b_18 rhigh w=5.02u l=9.34u b=4 ps=0.19u 
+R_pattern_19 a_19 b_19 rhigh w=4.64u l=9.14u b=8 ps=0.2u 
+R_pattern_20 a_20 b_20 rhigh w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_21 a_21 b_21 rhigh w=5.85u l=0.82u b=6 ps=0.19u 
+R_pattern_22 a_22 b_22 rhigh w=4.69u l=1.98u b=9 ps=0.19u 
+R_pattern_23 a_23 b_23 rhigh w=0.64u l=7.11u b=3 ps=0.19u 
+R_pattern_24 a_24 b_24 rhigh w=3.93u l=6.3u b=4 ps=0.19u 
+R_pattern_25 a_25 b_25 rhigh w=1.67u l=6.3u b=4 ps=0.2u 
+R_pattern_26 a_26 b_26 rhigh w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_27 a_27 b_27 rhigh w=0.64u l=5.4u b=4 ps=0.19u 
+R_pattern_28 a_28 b_28 rhigh w=4.69u l=3.03u b=4 ps=0.19u 
+R_pattern_29 a_29 b_29 rhigh w=5.85u l=9.34u b=2 ps=0.19u 
+R_pattern_30 a_30 b_30 rhigh w=5.1u l=9.14u b=2 ps=0.19u 
+R_pattern_31 a_31 b_31 rhigh w=4.64u l=0.82u b=9 ps=0.19u 
+R_pattern_32 a_32 b_32 rhigh w=5.02u l=1.98u b=3 ps=0.19u 
+R_pattern_33 a_33 b_33 rhigh w=5.02u l=3.03u b=8 ps=0.19u 
+R_pattern_34 a_34 b_34 rhigh w=4.64u l=5.4u b=6 ps=0.19u 
+R_pattern_35 a_35 b_35 rhigh w=5.1u l=7.11u b=8 ps=0.19u 
+R_pattern_36 a_36 b_36 rhigh w=5.85u l=6.3u b=9 ps=0.19u 
+R_pattern_37 a_37 b_37 rhigh w=4.69u l=0.82u b=2 ps=0.19u 
+R_pattern_38 a_38 b_38 rhigh w=0.64u l=9.34u b=9 ps=0.19u 
+R_pattern_39 a_39 b_39 rhigh w=3.93u l=9.14u b=9 ps=0.19u 
+R_pattern_40 a_40 b_40 rhigh w=1.67u l=1.98u b=4 ps=0.19u 
+R_pattern_41 a_41 b_41 rhigh w=1.67u l=0.82u b=3 ps=0.19u 
+R_pattern_42 a_42 b_42 rhigh w=3.93u l=3.03u b=6 ps=0.19u 
+R_pattern_43 a_43 b_43 rhigh w=0.64u l=1.98u b=6 ps=0.19u 
+R_pattern_44 a_44 b_44 rhigh w=4.69u l=5.4u b=8 ps=0.19u 
+R_pattern_45 a_45 b_45 rhigh w=5.85u l=9.14u b=4 ps=0.19u 
+R_pattern_46 a_46 b_46 rhigh w=5.1u l=6.3u b=3 ps=0.19u 
+R_pattern_47 a_47 b_47 rhigh w=4.64u l=7.11u b=2 ps=0.19u 
+R_pattern_48 a_48 b_48 rhigh w=5.02u l=6.3u b=4 ps=0.19u 
+R_pattern_49 a_49 b_49 rhigh w=5.02u l=9.14u b=4 ps=0.19u 
+R_pattern_50 a_50 b_50 rhigh w=4.64u l=9.34u b=3 ps=0.19u 
+R_pattern_51 a_51 b_51 rhigh w=5.1u l=1.98u b=4 ps=0.19u 
+R_pattern_52 a_52 b_52 rhigh w=5.85u l=7.11u b=4 ps=0.19u 
+R_pattern_53 a_53 b_53 rhigh w=4.69u l=9.34u b=4 ps=0.19u 
+R_pattern_54 a_54 b_54 rhigh w=0.64u l=3.03u b=4 ps=0.19u 
+R_pattern_55 a_55 b_55 rhigh w=3.93u l=0.82u b=4 ps=0.19u 
+R_pattern_56 a_56 b_56 rhigh w=1.67u l=9.34u b=6 ps=0.19u 
+R_pattern_57 a_57 b_57 rhigh w=5.02u l=5.4u b=2 ps=0.19u 
+R_pattern_58 a_58 b_58 rhigh w=1.67u l=7.11u b=9 ps=0.19u 
+R_pattern_59 a_59 b_59 rhigh w=4.64u l=3.03u b=4 ps=0.19u 
+R_pattern_60 a_60 b_60 rhigh w=1.67u l=0.82u b=8 ps=0.19u 
+R_pattern_61 a_61 b_61 rhigh w=3.93u l=5.4u b=3 ps=0.19u 
+R_pattern_62 a_62 b_62 rhigh w=0.64u l=9.14u b=8 ps=0.19u 
+R_pattern_63 a_63 b_63 rhigh w=4.69u l=6.3u b=6 ps=0.19u 
+R_pattern_64 a_64 b_64 rhigh w=5.85u l=1.98u b=4 ps=0.19u 
+R_pattern_65 a_65 b_65 rhigh w=5.1u l=0.82u b=6 ps=0.19u 
+R_pattern_66 a_66 b_66 rhigh w=5.02u l=0.82u b=9 ps=0.19u 
+R_pattern_67 a_67 b_67 rhigh w=1.67u l=0.82u b=4 ps=0.19u 
+R_pattern_68 a_68 b_68 rhigh w=5.1u l=1.98u b=8 ps=0.19u 
+R_pattern_69 a_69 b_69 rhigh w=5.1u l=9.14u b=4 ps=0.19u 
+R_pattern_70 a_70 b_70 rhigh w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_71 a_71 b_71 rhigh w=5.1u l=3.03u b=4 ps=0.19u 
+R_pattern_72 a_72 b_72 rhigh w=5.85u l=3.03u b=3 ps=0.19u 
+R_pattern_73 a_73 b_73 rhigh w=4.69u l=1.98u b=4 ps=0.19u 
+R_pattern_74 a_74 b_74 rhigh w=0.64u l=6.3u b=8 ps=0.19u 
+R_pattern_75 a_75 b_75 rhigh w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_76 a_76 b_76 rhigh w=3.93u l=7.11u b=2 ps=0.19u 
+R_pattern_77 a_77 b_77 rhigh w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_78 a_78 b_78 rhigh w=4.64u l=7.11u b=4 ps=0.19u 
+R_pattern_79 a_79 b_79 rhigh w=5.1u l=9.34u b=4 ps=0.19u
 .ENDS
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rppd.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rppd.cdl
index 7e42fe2a..ed71a67c 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rppd.cdl
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rppd.cdl
@@ -21,4 +21,85 @@ Rp2 net3 net4 rppd m=1 l=1u w=0.5u
 Rp3 net5 net6 rppd m=1 l=1.2u w=0.7u
 Rp4 net7 net8 rppd m=1 l=1u w=0.5u ps=0.2u b=1
 Rp5 net9 net10 rppd m=1 l=1.2u w=0.5u ps=0.2u b=2
+
+* Extra patterns
+R_pattern_1  a_1  b_1  rppd w=5.85u l=5.4u b=3 ps=0.2u 
+R_pattern_2  a_2  b_2  rppd w=1.67u l=9.14u b=6 ps=0.19u 
+R_pattern_3  a_3  b_3  rppd w=4.69u l=7.11u b=4 ps=0.19u 
+R_pattern_4  a_4  b_4  rppd w=5.02u l=0.82u b=4 ps=0.2u 
+R_pattern_5  a_5  b_5  rppd w=0.64u l=6.3u b=2 ps=0.2u 
+R_pattern_6  a_6  b_6  rppd w=4.64u l=1.98u b=4 ps=0.19u 
+R_pattern_7  a_7  b_7  rppd w=3.93u l=9.34u b=8 ps=0.19u 
+R_pattern_8  a_8  b_8  rppd w=5.1u l=3.03u b=9 ps=0.2u 
+R_pattern_9  a_9  b_9  rppd w=5.1u l=9.34u b=4 ps=0.2u 
+R_pattern_10 a_10 b_10 rppd w=3.93u l=1.98u b=2 ps=0.2u 
+R_pattern_11 a_11 b_11 rppd w=4.64u l=6.3u b=4 ps=0.19u 
+R_pattern_12 a_12 b_12 rppd w=0.64u l=0.82u b=4 ps=0.19u 
+R_pattern_13 a_13 b_13 rppd w=5.02u l=7.11u b=6 ps=0.2u 
+R_pattern_14 a_14 b_14 rppd w=4.69u l=9.14u b=3 ps=0.2u 
+R_pattern_15 a_15 b_15 rppd w=1.67u l=5.4u b=9 ps=0.19u 
+R_pattern_16 a_16 b_16 rppd w=5.85u l=3.03u b=8 ps=0.19u 
+R_pattern_17 a_17 b_17 rppd w=1.67u l=3.03u b=2 ps=0.19u 
+R_pattern_18 a_18 b_18 rppd w=5.02u l=9.34u b=4 ps=0.19u 
+R_pattern_19 a_19 b_19 rppd w=4.64u l=9.14u b=8 ps=0.2u 
+R_pattern_20 a_20 b_20 rppd w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_21 a_21 b_21 rppd w=5.85u l=0.82u b=6 ps=0.19u 
+R_pattern_22 a_22 b_22 rppd w=4.69u l=1.98u b=9 ps=0.19u 
+R_pattern_23 a_23 b_23 rppd w=0.64u l=7.11u b=3 ps=0.19u 
+R_pattern_24 a_24 b_24 rppd w=3.93u l=6.3u b=4 ps=0.19u 
+R_pattern_25 a_25 b_25 rppd w=1.67u l=6.3u b=4 ps=0.2u 
+R_pattern_26 a_26 b_26 rppd w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_27 a_27 b_27 rppd w=0.64u l=5.4u b=4 ps=0.19u 
+R_pattern_28 a_28 b_28 rppd w=4.69u l=3.03u b=4 ps=0.19u 
+R_pattern_29 a_29 b_29 rppd w=5.85u l=9.34u b=2 ps=0.19u 
+R_pattern_30 a_30 b_30 rppd w=5.1u l=9.14u b=2 ps=0.19u 
+R_pattern_31 a_31 b_31 rppd w=4.64u l=0.82u b=9 ps=0.19u 
+R_pattern_32 a_32 b_32 rppd w=5.02u l=1.98u b=3 ps=0.19u 
+R_pattern_33 a_33 b_33 rppd w=5.02u l=3.03u b=8 ps=0.19u 
+R_pattern_34 a_34 b_34 rppd w=4.64u l=5.4u b=6 ps=0.19u 
+R_pattern_35 a_35 b_35 rppd w=5.1u l=7.11u b=8 ps=0.19u 
+R_pattern_36 a_36 b_36 rppd w=5.85u l=6.3u b=9 ps=0.19u 
+R_pattern_37 a_37 b_37 rppd w=4.69u l=0.82u b=2 ps=0.19u 
+R_pattern_38 a_38 b_38 rppd w=0.64u l=9.34u b=9 ps=0.19u 
+R_pattern_39 a_39 b_39 rppd w=3.93u l=9.14u b=9 ps=0.19u 
+R_pattern_40 a_40 b_40 rppd w=1.67u l=1.98u b=4 ps=0.19u 
+R_pattern_41 a_41 b_41 rppd w=1.67u l=0.82u b=3 ps=0.19u 
+R_pattern_42 a_42 b_42 rppd w=3.93u l=3.03u b=6 ps=0.19u 
+R_pattern_43 a_43 b_43 rppd w=0.64u l=1.98u b=6 ps=0.19u 
+R_pattern_44 a_44 b_44 rppd w=4.69u l=5.4u b=8 ps=0.19u 
+R_pattern_45 a_45 b_45 rppd w=5.85u l=9.14u b=4 ps=0.19u 
+R_pattern_46 a_46 b_46 rppd w=5.1u l=6.3u b=3 ps=0.19u 
+R_pattern_47 a_47 b_47 rppd w=4.64u l=7.11u b=2 ps=0.19u 
+R_pattern_48 a_48 b_48 rppd w=5.02u l=6.3u b=4 ps=0.19u 
+R_pattern_49 a_49 b_49 rppd w=5.02u l=9.14u b=4 ps=0.19u 
+R_pattern_50 a_50 b_50 rppd w=4.64u l=9.34u b=3 ps=0.19u 
+R_pattern_51 a_51 b_51 rppd w=5.1u l=1.98u b=4 ps=0.19u 
+R_pattern_52 a_52 b_52 rppd w=5.85u l=7.11u b=4 ps=0.19u 
+R_pattern_53 a_53 b_53 rppd w=4.69u l=9.34u b=4 ps=0.19u 
+R_pattern_54 a_54 b_54 rppd w=0.64u l=3.03u b=4 ps=0.19u 
+R_pattern_55 a_55 b_55 rppd w=3.93u l=0.82u b=4 ps=0.19u 
+R_pattern_56 a_56 b_56 rppd w=1.67u l=9.34u b=6 ps=0.19u 
+R_pattern_57 a_57 b_57 rppd w=5.02u l=5.4u b=2 ps=0.19u 
+R_pattern_58 a_58 b_58 rppd w=1.67u l=7.11u b=9 ps=0.19u 
+R_pattern_59 a_59 b_59 rppd w=4.64u l=3.03u b=4 ps=0.19u 
+R_pattern_60 a_60 b_60 rppd w=1.67u l=0.82u b=8 ps=0.19u 
+R_pattern_61 a_61 b_61 rppd w=3.93u l=5.4u b=3 ps=0.19u 
+R_pattern_62 a_62 b_62 rppd w=0.64u l=9.14u b=8 ps=0.19u 
+R_pattern_63 a_63 b_63 rppd w=4.69u l=6.3u b=6 ps=0.19u 
+R_pattern_64 a_64 b_64 rppd w=5.85u l=1.98u b=4 ps=0.19u 
+R_pattern_65 a_65 b_65 rppd w=5.1u l=0.82u b=6 ps=0.19u 
+R_pattern_66 a_66 b_66 rppd w=5.02u l=0.82u b=9 ps=0.19u 
+R_pattern_67 a_67 b_67 rppd w=1.67u l=0.82u b=4 ps=0.19u 
+R_pattern_68 a_68 b_68 rppd w=5.1u l=1.98u b=8 ps=0.19u 
+R_pattern_69 a_69 b_69 rppd w=5.1u l=9.14u b=4 ps=0.19u 
+R_pattern_70 a_70 b_70 rppd w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_71 a_71 b_71 rppd w=5.1u l=3.03u b=4 ps=0.19u 
+R_pattern_72 a_72 b_72 rppd w=5.85u l=3.03u b=3 ps=0.19u 
+R_pattern_73 a_73 b_73 rppd w=4.69u l=1.98u b=4 ps=0.19u 
+R_pattern_74 a_74 b_74 rppd w=0.64u l=6.3u b=8 ps=0.19u 
+R_pattern_75 a_75 b_75 rppd w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_76 a_76 b_76 rppd w=3.93u l=7.11u b=2 ps=0.19u 
+R_pattern_77 a_77 b_77 rppd w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_78 a_78 b_78 rppd w=4.64u l=7.11u b=4 ps=0.19u 
+R_pattern_79 a_79 b_79 rppd w=5.1u l=9.34u b=4 ps=0.19u
 .ENDS
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rsil.cdl b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rsil.cdl
index 2d85c0dc..eabf0236 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rsil.cdl
+++ b/ihp-sg13g2/libs.tech/klayout/tech/lvs/testing/testcases/unit/res_devices/netlist/rsil.cdl
@@ -23,4 +23,85 @@ Rs4 net7 net8 rsil m=1 l=1u w=0.5u ps=0.2u b=1
 Rs5 net9 net10 rsil m=1 l=1.2u w=0.5u ps=0.2u b=2
 Rs6 net11 net12 rsil m=2 l=0.5u w=0.5u
 Rs7 net13 net14 rsil m=1 l=1u w=0.5u
+
+* Extra patterns
+R_pattern_1  a_1  b_1  rsil w=5.85u l=5.4u b=3 ps=0.2u 
+R_pattern_2  a_2  b_2  rsil w=1.67u l=9.14u b=6 ps=0.19u 
+R_pattern_3  a_3  b_3  rsil w=4.69u l=7.11u b=4 ps=0.19u 
+R_pattern_4  a_4  b_4  rsil w=5.02u l=0.82u b=4 ps=0.2u 
+R_pattern_5  a_5  b_5  rsil w=0.64u l=6.3u b=2 ps=0.2u 
+R_pattern_6  a_6  b_6  rsil w=4.64u l=1.98u b=4 ps=0.19u 
+R_pattern_7  a_7  b_7  rsil w=3.93u l=9.34u b=8 ps=0.19u 
+R_pattern_8  a_8  b_8  rsil w=5.1u l=3.03u b=9 ps=0.2u 
+R_pattern_9  a_9  b_9  rsil w=5.1u l=9.34u b=4 ps=0.2u 
+R_pattern_10 a_10 b_10 rsil w=3.93u l=1.98u b=2 ps=0.2u 
+R_pattern_11 a_11 b_11 rsil w=4.64u l=6.3u b=4 ps=0.19u 
+R_pattern_12 a_12 b_12 rsil w=0.64u l=0.82u b=4 ps=0.19u 
+R_pattern_13 a_13 b_13 rsil w=5.02u l=7.11u b=6 ps=0.2u 
+R_pattern_14 a_14 b_14 rsil w=4.69u l=9.14u b=3 ps=0.2u 
+R_pattern_15 a_15 b_15 rsil w=1.67u l=5.4u b=9 ps=0.19u 
+R_pattern_16 a_16 b_16 rsil w=5.85u l=3.03u b=8 ps=0.19u 
+R_pattern_17 a_17 b_17 rsil w=1.67u l=3.03u b=2 ps=0.19u 
+R_pattern_18 a_18 b_18 rsil w=5.02u l=9.34u b=4 ps=0.19u 
+R_pattern_19 a_19 b_19 rsil w=4.64u l=9.14u b=8 ps=0.2u 
+R_pattern_20 a_20 b_20 rsil w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_21 a_21 b_21 rsil w=5.85u l=0.82u b=6 ps=0.19u 
+R_pattern_22 a_22 b_22 rsil w=4.69u l=1.98u b=9 ps=0.19u 
+R_pattern_23 a_23 b_23 rsil w=0.64u l=7.11u b=3 ps=0.19u 
+R_pattern_24 a_24 b_24 rsil w=3.93u l=6.3u b=4 ps=0.19u 
+R_pattern_25 a_25 b_25 rsil w=1.67u l=6.3u b=4 ps=0.2u 
+R_pattern_26 a_26 b_26 rsil w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_27 a_27 b_27 rsil w=0.64u l=5.4u b=4 ps=0.19u 
+R_pattern_28 a_28 b_28 rsil w=4.69u l=3.03u b=4 ps=0.19u 
+R_pattern_29 a_29 b_29 rsil w=5.85u l=9.34u b=2 ps=0.19u 
+R_pattern_30 a_30 b_30 rsil w=5.1u l=9.14u b=2 ps=0.19u 
+R_pattern_31 a_31 b_31 rsil w=4.64u l=0.82u b=9 ps=0.19u 
+R_pattern_32 a_32 b_32 rsil w=5.02u l=1.98u b=3 ps=0.19u 
+R_pattern_33 a_33 b_33 rsil w=5.02u l=3.03u b=8 ps=0.19u 
+R_pattern_34 a_34 b_34 rsil w=4.64u l=5.4u b=6 ps=0.19u 
+R_pattern_35 a_35 b_35 rsil w=5.1u l=7.11u b=8 ps=0.19u 
+R_pattern_36 a_36 b_36 rsil w=5.85u l=6.3u b=9 ps=0.19u 
+R_pattern_37 a_37 b_37 rsil w=4.69u l=0.82u b=2 ps=0.19u 
+R_pattern_38 a_38 b_38 rsil w=0.64u l=9.34u b=9 ps=0.19u 
+R_pattern_39 a_39 b_39 rsil w=3.93u l=9.14u b=9 ps=0.19u 
+R_pattern_40 a_40 b_40 rsil w=1.67u l=1.98u b=4 ps=0.19u 
+R_pattern_41 a_41 b_41 rsil w=1.67u l=0.82u b=3 ps=0.19u 
+R_pattern_42 a_42 b_42 rsil w=3.93u l=3.03u b=6 ps=0.19u 
+R_pattern_43 a_43 b_43 rsil w=0.64u l=1.98u b=6 ps=0.19u 
+R_pattern_44 a_44 b_44 rsil w=4.69u l=5.4u b=8 ps=0.19u 
+R_pattern_45 a_45 b_45 rsil w=5.85u l=9.14u b=4 ps=0.19u 
+R_pattern_46 a_46 b_46 rsil w=5.1u l=6.3u b=3 ps=0.19u 
+R_pattern_47 a_47 b_47 rsil w=4.64u l=7.11u b=2 ps=0.19u 
+R_pattern_48 a_48 b_48 rsil w=5.02u l=6.3u b=4 ps=0.19u 
+R_pattern_49 a_49 b_49 rsil w=5.02u l=9.14u b=4 ps=0.19u 
+R_pattern_50 a_50 b_50 rsil w=4.64u l=9.34u b=3 ps=0.19u 
+R_pattern_51 a_51 b_51 rsil w=5.1u l=1.98u b=4 ps=0.19u 
+R_pattern_52 a_52 b_52 rsil w=5.85u l=7.11u b=4 ps=0.19u 
+R_pattern_53 a_53 b_53 rsil w=4.69u l=9.34u b=4 ps=0.19u 
+R_pattern_54 a_54 b_54 rsil w=0.64u l=3.03u b=4 ps=0.19u 
+R_pattern_55 a_55 b_55 rsil w=3.93u l=0.82u b=4 ps=0.19u 
+R_pattern_56 a_56 b_56 rsil w=1.67u l=9.34u b=6 ps=0.19u 
+R_pattern_57 a_57 b_57 rsil w=5.02u l=5.4u b=2 ps=0.19u 
+R_pattern_58 a_58 b_58 rsil w=1.67u l=7.11u b=9 ps=0.19u 
+R_pattern_59 a_59 b_59 rsil w=4.64u l=3.03u b=4 ps=0.19u 
+R_pattern_60 a_60 b_60 rsil w=1.67u l=0.82u b=8 ps=0.19u 
+R_pattern_61 a_61 b_61 rsil w=3.93u l=5.4u b=3 ps=0.19u 
+R_pattern_62 a_62 b_62 rsil w=0.64u l=9.14u b=8 ps=0.19u 
+R_pattern_63 a_63 b_63 rsil w=4.69u l=6.3u b=6 ps=0.19u 
+R_pattern_64 a_64 b_64 rsil w=5.85u l=1.98u b=4 ps=0.19u 
+R_pattern_65 a_65 b_65 rsil w=5.1u l=0.82u b=6 ps=0.19u 
+R_pattern_66 a_66 b_66 rsil w=5.02u l=0.82u b=9 ps=0.19u 
+R_pattern_67 a_67 b_67 rsil w=1.67u l=0.82u b=4 ps=0.19u 
+R_pattern_68 a_68 b_68 rsil w=5.1u l=1.98u b=8 ps=0.19u 
+R_pattern_69 a_69 b_69 rsil w=5.1u l=9.14u b=4 ps=0.19u 
+R_pattern_70 a_70 b_70 rsil w=5.1u l=5.4u b=4 ps=0.19u 
+R_pattern_71 a_71 b_71 rsil w=5.1u l=3.03u b=4 ps=0.19u 
+R_pattern_72 a_72 b_72 rsil w=5.85u l=3.03u b=3 ps=0.19u 
+R_pattern_73 a_73 b_73 rsil w=4.69u l=1.98u b=4 ps=0.19u 
+R_pattern_74 a_74 b_74 rsil w=0.64u l=6.3u b=8 ps=0.19u 
+R_pattern_75 a_75 b_75 rsil w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_76 a_76 b_76 rsil w=3.93u l=7.11u b=2 ps=0.19u 
+R_pattern_77 a_77 b_77 rsil w=3.93u l=7.11u b=4 ps=0.19u 
+R_pattern_78 a_78 b_78 rsil w=4.64u l=7.11u b=4 ps=0.19u 
+R_pattern_79 a_79 b_79 rsil w=5.1u l=9.34u b=4 ps=0.19u 
 .ENDS
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_lvs.lylvs b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_lvs.lylvs
index 2c59b5d0..41ed181b 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_lvs.lylvs
+++ b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_lvs.lylvs
@@ -36,6 +36,7 @@
  <text>
 
 require 'yaml'
+require 'open3'
 
 # Load LVS options from a YAML file
 #
@@ -82,6 +83,29 @@ def set_default_options(yaml_file_path)
   default_options
 end
 
+# check klayout version
+klayout_v, _ = Open3.capture2('klayout -b -v')
+klayout_v = klayout_v.split("\n")[0]
+klayout_v_list = []
+
+if klayout_v.empty?
+  raise StandardError, "KLayout is not found. Please make sure KLayout is installed."
+else
+  klayout_v_arr = klayout_v.split(" ")[-1].scan(/[^.]+/)
+  klayout_v_list = klayout_v_arr.map { |ele| ele.to_i }
+end
+
+if klayout_v_list.size &lt; 1 || klayout_v_list.size &gt; 3
+  raise StandardError, "Was not able to get KLayout version properly."
+elsif klayout_v_list.size &gt;= 2 || klayout_v_list.size &lt;= 3
+  if klayout_v_list[1] &lt; 29
+    puts "Using this KLayout version has not been assessed. Limits are unknown."
+    raise StandardError, "Prerequisites at a minimum: KLayout 0.29.0"
+  end
+end
+puts "Your KLayout version is: #{klayout_v}"
+
+# Get testing dir path
 dir_path = File.dirname(File.expand_path(__FILE__))
 
 ## reading the loaded gds file path
diff --git a/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_options.lym b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_options.lym
index d7050761..5d5b76cc 100644
--- a/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_options.lym
+++ b/ihp-sg13g2/libs.tech/klayout/tech/macros/sg13g2_options.lym
@@ -36,10 +36,35 @@
  <text>
  module SG13G2LVSOptions
   require 'yaml'
+  require 'open3'
   include RBA
 
   # Main function to manage LVS options
-  def self.main    
+  def self.main
+
+    # check klayout version
+    klayout_v, _ = Open3.capture2('klayout -b -v')
+    klayout_v = klayout_v.split("\n")[0]
+    klayout_v_list = []
+
+    if klayout_v.empty?
+      raise StandardError, "KLayout is not found. Please make sure KLayout is installed."
+    else
+      klayout_v_arr = klayout_v.split(" ")[-1].scan(/[^.]+/)
+      klayout_v_list = klayout_v_arr.map { |ele| ele.to_i }
+    end
+
+    if klayout_v_list.size &lt; 1 || klayout_v_list.size &gt; 3
+      raise StandardError, "Was not able to get KLayout version properly."
+    elsif klayout_v_list.size &gt;= 2 || klayout_v_list.size &lt;= 3
+      if klayout_v_list[1] &lt; 29
+        puts "Using this KLayout version has not been assessed. Limits are unknown."
+        raise StandardError, "Prerequisites at a minimum: KLayout 0.29.0"
+      end
+    end
+
+    puts "Your KLayout version is: #{klayout_v}"
+
     # Construct the absolute path to the YAML file
     yaml_file_path = "#{__dir__}/lvs_options.yml"
 
@@ -113,14 +138,14 @@
   #
   # Returns a list contains all top cell names
   def self.get_top_cell_names
-    top_cells = []
+    cells = []
     layout = RBA::Layout.new
     layout.read(Pathname.new(RBA::CellView.active.filename))
 
-    layout.top_cells.each do |cell|
-      top_cells.push(cell.name)
+    layout.each_cell do |cell|
+      cells.push(cell.name)
     end
-    top_cells
+    cells
   end
 
   # Create a dialog box for selecting LVS options