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IO library fixes & improvements #109
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@sergeiandreyev @KrzysztofHerman |
BTW, this thus contain fix for #101 |
I only now see that Boris did still find that the bulk is connected to iovdd; so wait with merging until this is clarified. |
Hello Staf, let's have a sync-up on IO cells with Alexey Balashov, to be all on the same page |
@FatsieFS , we just had a meeting with Mabrains team who are developing KLayout LVS for our OpenPDK.. |
@FatsieFS IOPadVdd has missing slits on M2. Maximum width without slits is 30u. |
* IOPadVdd: remove spurious diodes from netlist and update IOPadVdd internal connections in layout to fix reported problem. Previous layout did not have proper ESD on Vdd pin and also resulted in iovdd to iovss static current. * Update performance simulation after fixing the diode model. Removes the NA values present in the result tables. * Set LEF version to 5.7 * Fix indentation in dummy liberty file. Signed-off-by: Staf Verhaegen <staf.verhaegen@chipflow.io>
I updated patch with fixed gds. I did fix it but seems I did not properly update the gds file in the patch. |
@stafverhaegen-chipflow just tried your new GDS and looks good to me! |
@dnltz does it solve the problem for you? Shall we merge ? |
@KrzysztofHerman Slt.c is missing in the Open PDK rules but there is no area wider then 30u anymore. Should be fine. |
@KrzysztofHerman |
This PR contains critical fix for the IOPadVdd cell. Previous gds should not be used anymore for new tape-outs.
For the rest some small improvements to the generated files and docs.