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Merge pull request #97 from mabrains/dev
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Fix some of the open issues
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KrzysztofHerman authored May 2, 2024
2 parents b5c6abe + 764692d commit 7e620a9
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Showing 8 changed files with 11 additions and 11 deletions.
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Expand Up @@ -296,8 +296,8 @@ class CustomReader < RBA::NetlistSpiceReaderDelegate
device.set_parameter('b', params['B'] || 0.0)
device.set_parameter('m', params['M'] || 1.0)
else
device.set_parameter('W', (params['W'] || 0.0) * (params['M'] || 1.0) * 1e6)
device.set_parameter('L', (params['L'] || 0.0) * (params['S'] || 1.0) * 1e6)
device.set_parameter('W', (params['W'] || params['WIDTH'] || 0.0) * (params['M'] || 1.0) * 1e6)
device.set_parameter('L', (params['L'] || params['LENGTH'] || 0.0) * (params['S'] || 1.0) * 1e6)
device.set_parameter('R', (params['R'] || 0.0) * (params['S'] || 1.0) / (params['M'] || 1.0))
end
end
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Expand Up @@ -23,20 +23,20 @@

logger.info('Starting RESISTOR DERIVATIONS')

polyres_exclude = activ_drw.join(nwell_drw).join(pwell_block)
.join(nsd_block).join(nbulay_drw).join(thickgateox_drw)
.join(heattrans_drw).join(trans_drw).join(emwind_drw)
.join(emwihv_drw).join(mim_drw).join(activ_mask)
.join(recog_diode).join(recog_esd).join(ind_drw)
.join(ind_pin).join(substrate_drw)
polyres_exclude = activ_drw.join(pwell_block).join(nsd_block)
.join(nbulay_drw).join(thickgateox_drw).join(heattrans_drw)
.join(trans_drw).join(emwind_drw).join(emwihv_drw)
.join(mim_drw).join(activ_mask).join(recog_diode)
.join(recog_esd).join(ind_drw).join(ind_pin)
.join(substrate_drw)

# ==============
# ---- POLY ----
# ==============

## polyres
polyres_mk = polyres_drw.and(heatres_drw).and(extblock_drw)
.and(pwell).interacting(gatpoly_drw).not(polyres_exclude)
.interacting(gatpoly_drw).not(polyres_exclude)

## rhigh
rhigh_res = polyres_mk.and(psd_drw).and(nsd_drw).and(salblock_drw)
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Expand Up @@ -18,5 +18,5 @@
.SUBCKT lvsres
Rm1 net1 net2 lvsres l=1u w=5u
Rm2 net3 net4 lvsres l=1.5u w=5u
Rm3 net5 net6 lvsres l=1u w=6u
Rm3 net5 net6 lvsres length=1u width=6u
.ENDS
2 changes: 1 addition & 1 deletion ihp-sg13g2/libs.tech/klayout/tech/macros/lvs_options.yml
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Expand Up @@ -5,9 +5,9 @@ netlist: ''
spice_net: true
top_cell_name: ''
spice_comment: false
netlist_simplify: true
net_only: false
top_lvl_pins: false
netlist_simplify: true
combine: false
purge: false
purge_nets: false
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