Design and Implementation of I2C and SPI Protocols

AIM: The aim of the project is set as designing and development of I2C and SPI protocols in a simulation environment using verilog

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Description:

I2C:

Inter-Integrated Circuit or Two wire interface is a serial Communication Protocol which is half Duplex. Widely used for short distance, intra-board communication. I2C connects devices like Microcontrollers, EEPROMS, A/D and D/A converters, I/O interfaces and other similar peripheral interfaces in Embedded Systems.

TRANSMISSION OF DATA IN I2C BUS

1. IDEAL STATE: When no data is transmitted between master and slave then SDA and SCL lines are at high logic.
2. Start Condition: SDA line goes from high logic to low logic while SCL line remains at high logic. This is called "start signal".
3. Slave Address: 7-bit address of target slave is transmitted.
4. ACK: Slave will generate a 1-bit signal to acknowledge master.
5. Data Transfer: 8-bit data is transmitted over SDA line in an order such that MSB is transmitted first and LSB at last.
6. ACK2: An acknowledge signal is again generated by the slave when a byte (8-bit) is received from mater.
7. Stop Condition: SDA line goes from low logic to high logic and SCL line remains high, this is called as "stop signal".

SPI:

Serial Peripheral Interface is a synchronous serial communication interface specification used for short-distance communication primarily in embedded systems. Chips, microprocessors and FGPA based designs uses SPI to communicate between internal components in a more faster and efficient way.

Some important featues of SPI protocol:

• Serial Protocol Communication
• Four wire interface
• Full-Duplex
• Can transmit data up to 60Mbps

1. Data transmission: The SPI bus operates with single master device and one or multiple slave devices.
2. SPI operating modes: Usually there are four modes of operation. * Mode 1: Clock Polarity- 0 and Data captured at rising edge (1) * Mode 2: Clock Polarity- 0 and Data captured at falling edge (0) * Mode 3: Clock Polarity- 1 and Data captured at falling edge (0) * Mode 4: Clock Polarity- 1 and Data captured at rising edge (1) In our design, SPI mode can be configured easily, by selecting clock phase and polarity.

Implementation:

1. Implementation of I2C master and slave:

Initially, we focussed on I2C master design. First, i2c master FSM was written, and it was written in verilog Hardware Description language (HDL). Later, test bench was written to verify its working. Then we moved on to implement i2c slave. Finally, test bench was written to analyse the communication between i2c master and slave. We did functional simulation with various test inputs to verify i2c master and slave communication.

2. Implementation of SPI master and slave:

We haven't used any state machine in our SPI design. SPI master and slave generates its own clock based on the mode of operation choosen. We can specify mode of operation in testbench. We first started with master design. Then, we focussed on slave design. In fact, it's easier to design slave once we are done with master design. Here, we came across clock domain crossing concept. In order to capture data at active edge of spi clk, we expanded the signal using temperorary registers. Finally, we integrated both of these modules to test its working.