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Guray00 · Dec 9, 2023 · bc8c7e5 · bc8c7e5
1 parent c50b61f
commit bc8c7e5
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/SECONDO ANNO/I SEMESTRE/Reti Logiche/Esami/Scritti/2021/2021-06-09/Verilog/sintesi.v b/SECONDO ANNO/I SEMESTRE/Reti Logiche/Esami/Scritti/2021/2021-06-09/Verilog/sintesi.v
@@ -238,7 +238,7 @@ module ParteControllo(
         (STAR==S12)? 14'b00000000010000:
         (STAR==S13)? 14'b00100000000000:
         (STAR==S14)? 14'b000000001X1000:
-        /*default*/  14'b00XXXXXXXXXXXX;
+        /*default*/  14'bXXXXXXXXXXXXXX;
 
     always @(reset_ == 0) #1 STAR <= S0;
 

diff --git a/SECONDO ANNO/I SEMESTRE/Reti Logiche/Laboratori/Esercitazioni Verilog/8/sintesi.v b/SECONDO ANNO/I SEMESTRE/Reti Logiche/Laboratori/Esercitazioni Verilog/8/sintesi.v
@@ -238,7 +238,7 @@ module ParteControllo(
         (STAR==S12)? 14'b00000000010000:
         (STAR==S13)? 14'b00100000000000:
         (STAR==S14)? 14'b000000001X1000:
-        /*default*/  14'b00XXXXXXXXXXXX;
+        /*default*/  14'bXXXXXXXXXXXXXX;
 
     always @(reset_ == 0) #1 STAR <= S0;