diff --git a/GorgonMeducer.perf_counter.pdsc b/GorgonMeducer.perf_counter.pdsc index 3141cdc..5c5d9b2 100644 --- a/GorgonMeducer.perf_counter.pdsc +++ b/GorgonMeducer.perf_counter.pdsc @@ -6,7 +6,7 @@ A dedicated performance counter for the Cortex-M Systick. It shares the SysTick with users' original SysTick function without interfering with it. This library will bring new functionalities, such as performance counter, APIs for delay, clock() defined in time.h etc. https://raw.githubusercontent.com/GorgonMeducer/perf_counter/CMSIS-Pack/cmsis-pack/ https://github.com/GorgonMeducer/perf_counter/issues - lib/LICENSE + LICENSE - + A dedicated performance counter for Cortex-M systick. - - - + + + + + + #define __PERF_COUNTER__ 1 - #define __PERF_COUNTER_CFG_USE_SYSTICK_WRAPPER__ 1 - + + A dedicated performance counter for Cortex-M systick. - - - + #define __PERF_COUNTER__ 1 + + + + A user define system timer + + + + + + +#define __RTE_PERFC_PORTING_USER_DEFINED__ 1 + -#define __PERF_COUNTER_CFG_USE_SYSTICK_WRAPPER__ 1 +#define __PERFC_USE_USER_CUSTOM_PORTING__ 1 +#define __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ 1 +#define __PERFC_CFG_PORTING_INCLUDE__ "perfc_port_user.h" + - - A dedicated performance counter for Cortex-M systick. + + Using the Performande Monitor Unit - - + + -#define __PERF_COUNTER__ 1 +#define __RTE_PERFC_PORTING_PMU__ 1 + + + +#define __PERFC_USE_PMU_PORTING__ 1 +#define __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ 1 +#define __PERFC_CFG_PORTING_INCLUDE__ "perfc_port_pmu.h" + + - + Coremark - - + + @@ -331,7 +366,7 @@ - + A Patch for RTX5 @@ -343,7 +378,7 @@ - + A Patch for FreeRTOS @@ -366,7 +401,7 @@ extern void __freertos_evr_on_task_switched_in(void *ptTCB, unsigned int uxTopPr - + A Patch for RT-Thread @@ -384,7 +419,7 @@ extern void __rt_thread_scheduler_hook(struct rt_thread *from, struct rt_thread - + A Patch for ThreadX diff --git a/README.md b/README.md index 96d8985..a205d14 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# perf_counter (v2.2.4) +# perf_counter (v2.3.0) A dedicated performance counter for Cortex-M Systick. It shares the SysTick with users' original SysTick function(s) without interfering with it. This library will bring new functionalities, such as performance counter,` delay_us` and `clock()` service defined in `time.h`. ### Features: @@ -10,10 +10,15 @@ A dedicated performance counter for Cortex-M Systick. It shares the SysTick with - Measures **RAW / True** cycles used for specified code segment inside a thread, **i.e. scheduling cost are removed**. - Measure **RAW/True** cycles used for a data-process-path across multiple threads. - **Easy to use** - - Helper macros: `__cycleof__()` , `__super_loop_monitor__()` etc. + - Helper macros: `__cycleof__()` , `__super_loop_monitor__()` , `__cpu_usage__()`, `__cpu_perf__()` etc. - Helper functions: `start_cycle_counter()`, `stop_cycle_counter()` etc. -- **Support ALL Cortex-M processors** - - Including **Cortex-M85** and Star-MC1 +- Enable a broader processor architecture support + - **Support ALL Cortex-M processors** + - SysTick + - **[new]**Performance Monitor Unit (PMU) + + - **[new]**Easy to port to a different architecture with a porting template + - **Provide Free Services** - Do **NOT** interfer with existing SysTick based applications - **Support ALL arm compilers** @@ -26,13 +31,12 @@ A dedicated performance counter for Cortex-M Systick. It shares the SysTick with - **CMSIS-Pack is available** - **RT-Thread package is avaialble** - **Time based services** - - `delay_us()` and `delay_ms()` + - **[new]**`delay_us()` and `delay_ms()` with **64bit return value**. - Provides Timestamp services via `get_system_ticks()`, `get_system_us` and `get_system_ms()`. - **Support both RTOS and bare-metal environments** - Support SysTick Reconfiguration - Support changing System Frequency - - **[new]** Support stack-overflow detection in RTOS environment via `perfc_check_task_stack_canary_safe()` - + - Support stack-overflow detection in RTOS environment via `perfc_check_task_stack_canary_safe()` - **Utilities for C language enhancement** - Macros to detect compilers, e.g. `__IS_COMPILER_ARM_COMPILER_6__`, `__IS_COMPILER_LLVM__` etc. - Macro to create atomicity for specified code block, i.e. `__IRQ_SAFE{...}` @@ -60,7 +64,7 @@ __cycleof__(, [User Code, see ref 1]) { } ``` -Here, [**ref 1**] is a small user code to read the measurement result via a local variable `__cycle_count__` for perl lovers, you can also use "`_`" to read the result. This User Code is optional. If you don't put anything here, the measured result will be shown with a `printf()`. +Here, [**ref 1**] is a small user code to read the measurement result via a local variable `__cycle_count__` . This User Code is optional. If you don't put anything here, the measured result will be shown with a `__perf_counter_printf__`. #### **Example 1:** Simple measurement with printf @@ -99,9 +103,123 @@ The result is read out from `__cycle_count__`and used in other place: ![image-20220509004714845](./documents/pictures/__cycleof___output_non_printf) +### 1.2 Performance Analysis + +#### 1.2.1 CPU Usage + +For both bare-metal and OS environment, you can measure the CPU Usage with macro `__cpu_usage__()` for a given code segment as long as it is executed repeatedly. + +**Syntax** + +```c +__cycleof__(, [User Code, see ref 1]) { + //! target code segment of measurement + ... +} +``` + +Here, [**ref 1**] is a small user code to read the measurement result via a local variable `__usage__`. This User Code is optional. If you don't put anything here, the measured result will be shown with a `__perf_counter_printf__`. + +##### **Example 1: the following code will show 30% of CPU Usage:** + +```c +void main(void) +{ + ... + while (1) { + __cpu_usage__(10) { + delay_us(30000); + } + delay_us(70000); + } + ... +} +``` + +##### Example 2: Read measurement result via `__usage__` + +```c +void main(void) +{ + ... + while (1) { + + float fUsage = 0.0f; + __cpu_usage__(10, { + fUsage = __usage__; /*< "__usage__" stores the result */ + }) { + delay_us(30000); + } + printf("task 1 cpu usage %3.2f %%\r\n", (double)fUsage); + + delay_us(70000); + } + ... +} +``` + +NOTE: The `__usage__` stores the percentage information. + + + +#### 1.2.2 Cycle per Instruction and L1 DCache Miss Rate + +For **Armv8.1-m** processors that implement the **PMU**, it is easy to measure the **CPI** (Cycle per Instruction) and **L1 DCache miss rate** with the macro `__cpu_perf__()`. + +**Syntax**: + +```c +__cpu_perf__(, [User Code, see ref 1]) { + //! target code segment of measurement + ... +} +``` + +Here, [**ref 1**] is a small user code to read the measurement result via a local **struct** variable `__PERF_INFO__` . This User Code is optional. If you don't put anything here, the measured result will be shown with a `__perf_counter_printf__`. The prototype of the `__PERF_INFO__` is shown below: + +```c +struct { + uint64_t dwNoInstr; /* number of instruction executed */ + uint64_t dwNoMemAccess; /* number of memory access */ + uint64_t dwNoL1DCacheRefill; /* number of L1 DCache Refill */ + int64_t lCycles; /* number of CPU cycles */ + uint32_t wInstrCalib; + uint32_t wMemAccessCalib; + float fCPI; /* Cycle per Instruction */ + float fDCacheMissRate; /* L1 DCache miss rate in percentage */ +} __PERF_INFO__; +``` + +For example, when insert user code, you can read CPI from `__PERF_INFO__.fCPI`. + +**Example 1: measure the Coremark** +```c +void main(void) +{ + init_cycle_counter(false); + + printf("Run coremark\r\n"); + +#ifdef __PERF_COUNTER_COREMARK__ + __cpu_perf__("Coremark") { + coremark_main(); + } +#endif + + while(1) { + __NOP(); + } +} +``` + +The result might look like the following: + +![](./documents/pictures/__cpu_perf__output.png) -### 1.2 Timestamp + + +### 1.3 Timestamp You can get the system timestamp (since the initialization of perf_counter service) via function `get_system_ticks()` and `get_system_ms()`. @@ -172,7 +290,7 @@ This example shows how to use the delta value of `get_system_ticks()` to measure -### 1.3 Timer Services +### 1.4 Timer Services perf_counter provides the basic timer services for delaying a given period of time and polling-for-timeout. For example: @@ -193,7 +311,7 @@ while(1) { -### 1.4 Work with EventRecorder in MDK +### 1.5 Work with EventRecorder in MDK If you are using EventRecorder in MDK, once you deployed the `perf_counter`, it will provide the timer service for EventRecorder by implenting the following functions: `EventRecorderTimerSetup()`, `EventRecorderTimerGetFreq()` and `EventRecorderTimerGetCount()`. @@ -213,9 +331,9 @@ Please set the macro `EVENT_TIMESTAMP_SOURCE` to `3` to suppress it. -### 1.5 On System Environment Changing +### 1.6 On System Environment Changing -#### 1.5.1 System Frequency Changing +#### 1.6.1 System Frequency Changing If you want to change the System Frequency, **after** the change, make sure: @@ -225,7 +343,7 @@ If you want to change the System Frequency, **after** the change, make sure: -#### 1.5.2 Reconfigure the SysTick +#### 1.6.2 Reconfigure the SysTick Some systems (e.g. FreeRTOS) might reconfigure the systick timer to fulfil the requirement of their feature. To support this: @@ -250,7 +368,10 @@ git clone https://github.com/GorgonMeducer/perf_counter.git ``` 2. Add including path for `perf_counter` folder -3. Add `perf_counter.c` to your compilation +3. Add `perf_counter.c` to your compilation. + +> **NOTE**: Please do **NOT** add any assembly source files of this `perf_counter` library to your compilation, i.e. `systick_wrapper_gcc.S`, `systick_wrapper_gnu.s` or `systick_wrapper_ual.s`. + 4. Include `perf_counter.h` in corresponding c source file: ```c @@ -259,13 +380,13 @@ git clone https://github.com/GorgonMeducer/perf_counter.git 5. Make sure your system contains the CMSIS (with a version 5.7.0 or above) as `perf_counter.h` includes `cmsis_compiler.h`. -6. Call the function `user_code_insert_to_systick_handler()` in your `SysTick_Handler()` +6. Call the function `perfc_port_insert_to_system_timer_insert_ovf_handler()` in your `SysTick_Handler()` ```c void SysTick_Handler(void) { ... - user_code_insert_to_systick_handler(); + perfc_port_insert_to_system_timer_insert_ovf_handler(); ... } ``` diff --git a/benchmark/coremark_port/core_main.c b/benchmark/coremark_port/core_main.c index db5cd54..2adb3d0 100644 --- a/benchmark/coremark_port/core_main.c +++ b/benchmark/coremark_port/core_main.c @@ -22,6 +22,15 @@ Original Author: Shay Gal-on */ #include "coremark.h" +#if defined(__clang__) +# pragma clang diagnostic ignored "-Wunknown-warning-option" +# pragma clang diagnostic ignored "-Wreserved-identifier" +# pragma clang diagnostic ignored "-Wconditional-uninitialized" +# pragma clang diagnostic ignored "-Wsign-conversion" +# pragma clang diagnostic ignored "-Wimplicit-int-conversion" +#endif + + /* Function: iterate Run the benchmark for a specified number of iterations. @@ -104,6 +113,9 @@ char *mem_name[3] = { "Static", "Heap", "Stack" }; */ +__attribute__((used)) +volatile double dfCoremarkScore = 0.0f; + #if MAIN_HAS_NOARGC MAIN_RETURN_TYPE coremark_main(void) @@ -409,6 +421,8 @@ for (i = 0; i < MULTITHREAD; i++) double dfResult = (double)((double)1000000 * (double)default_num_contexts*results[0].iterations / (double)total_time); + dfCoremarkScore = dfResult; + ee_printf( "CoreMark 1.0 : %f / %s %s", dfResult, COMPILER_VERSION, diff --git a/documents/pictures/__cpu_perf__output.png b/documents/pictures/__cpu_perf__output.png new file mode 100644 index 0000000..b9c241f Binary files /dev/null and b/documents/pictures/__cpu_perf__output.png differ diff --git a/example/RTE/Device/ARMCM0/ARMCM0_ac6.sct b/example/RTE/Device/ARMCM0/ARMCM0_ac6.sct new file mode 100644 index 0000000..5300b01 --- /dev/null +++ b/example/RTE/Device/ARMCM0/ARMCM0_ac6.sct @@ -0,0 +1,80 @@ +#! armclang -E --target=arm-arm-none-eabi -mcpu=cortex-m0 -xc +; command above MUST be in first line (no comment above!) + +/* +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- +*/ + +/*--------------------- Flash Configuration ---------------------------------- +; Flash Configuration +; Flash Base Address <0x0-0xFFFFFFFF:8> +; Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __ROM_BASE 0x00000000 +#define __ROM_SIZE 0x00080000 + +/*--------------------- Embedded RAM Configuration --------------------------- +; RAM Configuration +; RAM Base Address <0x0-0xFFFFFFFF:8> +; RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __RAM_BASE 0x20000000 +#define __RAM_SIZE 0x00040000 + +/*--------------------- Stack / Heap Configuration --------------------------- +; Stack / Heap Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + *----------------------------------------------------------------------------*/ +#define __STACK_SIZE 0x00000200 +#define __HEAP_SIZE 0x00000C00 + +/* +;------------- <<< end of configuration section >>> --------------------------- +*/ + + +/*---------------------------------------------------------------------------- + User Stack & Heap boundary definition + *----------------------------------------------------------------------------*/ +#define __STACK_TOP (__RAM_BASE + __RAM_SIZE) /* starts at end of RAM */ +#define __HEAP_BASE (AlignExpr(+0, 8)) /* starts after RW_RAM section, 8 byte aligned */ + + +/*---------------------------------------------------------------------------- + Scatter File Definitions definition + *----------------------------------------------------------------------------*/ +#define __RO_BASE __ROM_BASE +#define __RO_SIZE __ROM_SIZE + +#define __RW_BASE __RAM_BASE +#define __RW_SIZE (__RAM_SIZE - __STACK_SIZE - __HEAP_SIZE) + + +LR_ROM __RO_BASE __RO_SIZE { ; load region size_region + ER_ROM __RO_BASE __RO_SIZE { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + RW_NOINIT __RW_BASE UNINIT __RW_SIZE { + *(.bss.noinit) + } + + RW_RAM AlignExpr(+0, 8) (__RW_SIZE - AlignExpr(ImageLength(RW_NOINIT), 8)) { + *(+RW +ZI) + } + +#if __HEAP_SIZE > 0 + ARM_LIB_HEAP __HEAP_BASE EMPTY __HEAP_SIZE { ; Reserve empty region for heap + } +#endif + + ARM_LIB_STACK __STACK_TOP EMPTY -__STACK_SIZE { ; Reserve empty region for stack + } +} diff --git a/example/RTE/Device/ARMCM0/startup_ARMCM0.c b/example/RTE/Device/ARMCM0/startup_ARMCM0.c new file mode 100644 index 0000000..fb32110 --- /dev/null +++ b/example/RTE/Device/ARMCM0/startup_ARMCM0.c @@ -0,0 +1,146 @@ +/****************************************************************************** + * @file startup_ARMCM0.c + * @brief CMSIS-Core(M) Device Startup File for a Cortex-M0 Device + * @version V2.0.3 + * @date 31. March 2020 + ******************************************************************************/ +/* + * Copyright (c) 2009-2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCM0) + #include "ARMCM0.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler (void); + void Default_Handler(void); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +/* Exceptions */ +void NMI_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void HardFault_Handler (void) __attribute__ ((weak)); +void SVC_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void PendSV_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void SysTick_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + +void Interrupt0_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt1_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt2_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt3_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt4_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt5_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt6_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt7_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt8_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); +void Interrupt9_Handler (void) __attribute__ ((weak, alias("Default_Handler"))); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +extern const VECTOR_TABLE_Type __VECTOR_TABLE[48]; + const VECTOR_TABLE_Type __VECTOR_TABLE[48] __VECTOR_TABLE_ATTRIBUTE = { + (VECTOR_TABLE_Type)(&__INITIAL_SP), /* Initial Stack Pointer */ + Reset_Handler, /* Reset Handler */ + NMI_Handler, /* -14 NMI Handler */ + HardFault_Handler, /* -13 Hard Fault Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + 0, /* Reserved */ + SVC_Handler, /* -5 SVCall Handler */ + 0, /* Reserved */ + 0, /* Reserved */ + PendSV_Handler, /* -2 PendSV Handler */ + SysTick_Handler, /* -1 SysTick Handler */ + + /* Interrupts */ + Interrupt0_Handler, /* 0 Interrupt 0 */ + Interrupt1_Handler, /* 1 Interrupt 1 */ + Interrupt2_Handler, /* 2 Interrupt 2 */ + Interrupt3_Handler, /* 3 Interrupt 3 */ + Interrupt4_Handler, /* 4 Interrupt 4 */ + Interrupt5_Handler, /* 5 Interrupt 5 */ + Interrupt6_Handler, /* 6 Interrupt 6 */ + Interrupt7_Handler, /* 7 Interrupt 7 */ + Interrupt8_Handler, /* 8 Interrupt 8 */ + Interrupt9_Handler /* 9 Interrupt 9 */ + /* Interrupts 10..31 are left out */ +}; + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__NO_RETURN void Reset_Handler(void) +{ + SystemInit(); /* CMSIS System Initialization */ + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wmissing-noreturn" +#endif + +/*---------------------------------------------------------------------------- + Hard Fault Handler + *----------------------------------------------------------------------------*/ +void HardFault_Handler(void) +{ + while(1); +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void Default_Handler(void) +{ + while(1); +} + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#endif + diff --git a/example/example.uvmpw b/example/example.uvmpw index 3cb8598..56eb5bd 100644 --- a/example/example.uvmpw +++ b/example/example.uvmpw @@ -5,7 +5,7 @@
### uVision Project, (C) Keil Software
- WorkSpace + Y:\Work\git\perf_counter\example\example.uvmpw .\example.uvprojx @@ -15,7 +15,6 @@ .\gcc_example.uvprojx - 1 diff --git a/example/example.uvoptx b/example/example.uvoptx index 4e58ca8..30fd0c7 100644 --- a/example/example.uvoptx +++ b/example/example.uvoptx @@ -75,7 +75,7 @@ 1 0 - 0 + 1 7 @@ -130,7 +130,7 @@ 0 DbgFM - -I -S"System Generator:FVP_MPS2_Cortex_M0_MDK" -L"armcortexm0ct" -O4102 -C0 -MC".\FVP\MPS2_Cortex-M\FVP_MPS2_Cortex-M0_MDK.exe" -MF -PF -MA + -I -S"System Generator:cpu_core" -L"armcortexm0ct" -O4102 -C0 -MC".\VHT\VHT_MPS2_Cortex-M0.exe" -MF -PF -MA 0 @@ -195,7 +195,7 @@ C:\Users\gabriel\AppData\Local\Arm\Packs\Keil\ARM_Compiler\1.7.2\EventRecorder.scvd - Keil.ARM_Compiler.1.7.2 + Keil::ARM_Compiler@1.7.2 1 @@ -204,7 +204,7 @@ 0 1 - 0 + 1 0 0 0 @@ -297,7 +297,7 @@ 1 0 - 1 + 0 7 @@ -768,12 +768,24 @@ 2 7 - 4 + 1 + 0 + 0 + 0 + ..\perfc_port_default.c + perfc_port_default.c + 0 + 0 + + + 2 + 8 + 5 0 0 0 - ..\lib\perf_counter.lib - perf_counter.lib + ..\perfc_port_default.h + perfc_port_default.h 0 0 diff --git a/example/example.uvprojx b/example/example.uvprojx index bfde3e3..ddf1f72 100644 --- a/example/example.uvprojx +++ b/example/example.uvprojx @@ -10,7 +10,7 @@ example_arm_compiler_6 0x4 ARM-ADS - 6210000::V6.21::.\ArmCompilerforEmbedded6.21 + 6210000::V6.21::ARMCLANG 1 @@ -408,57 +408,6 @@ perf_counter.c 1 ..\perf_counter.c - - - 2 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - 2 - 2 - 2 - 2 - 2 - 0 - 0 - 2 - 2 - 2 - 2 - 2 - - - - - - - - - perf_counter.h @@ -469,49 +418,16 @@ systick_wrapper_ual.s 2 ..\systick_wrapper_ual.s - - - 2 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 2 - 0 - - - - - - - - - - perf_counter.lib - 4 - ..\lib\perf_counter.lib + perfc_port_default.c + 1 + ..\perfc_port_default.c + + + perfc_port_default.h + 5 + ..\perfc_port_default.h @@ -533,14 +449,14 @@ library 0x4 ARM-ADS - 6190000::V6.19::ARMCLANG + 6210000::V6.21::ARMCLANG 1 ARMCM0 ARM - ARM.CMSIS.5.9.0 - http://www.keil.com/pack/ + ARM.Cortex_DFP.1.0.0 + https://www.keil.com/pack/ IRAM(0x20000000,0x00020000) IROM(0x00000000,0x00040000) CPUTYPE("Cortex-M0") CLOCK(12000000) ESEL ELITTLE @@ -860,7 +776,7 @@ 0 0 - + -Wno-undef @@ -1012,28 +928,14 @@ ..\systick_wrapper_ual.s - perf_counter.lib - 4 - ..\lib\perf_counter.lib - - - 2 - 0 - 0 - 0 - 0 - 0 - 2 - 2 - 2 - 2 - 11 - - - 1 - - - + perfc_port_default.c + 1 + ..\perfc_port_default.c + + + perfc_port_default.h + 5 + ..\perfc_port_default.h @@ -1692,9 +1594,14 @@ - perf_counter.lib - 4 - ..\lib\perf_counter.lib + perfc_port_default.c + 1 + ..\perfc_port_default.c + + + perfc_port_default.h + 5 + ..\perfc_port_default.h @@ -1757,17 +1664,27 @@ - + + + + + + + + + + + + + - - @@ -1798,20 +1715,36 @@ + + RTE\Device\ARMCM0\ARMCM0_ac6.sct + + + + + + + + + RTE\Device\ARMCM0\startup_ARMCM0.c + + + + + + + RTE\Device\ARMCM0\startup_ARMCM0.s - - - + RTE\Device\ARMCM0\system_ARMCM0.c - - + + diff --git a/example/gcc_example.uvoptx b/example/gcc_example.uvoptx index 6aff661..9c7c0b3 100644 --- a/example/gcc_example.uvoptx +++ b/example/gcc_example.uvoptx @@ -561,6 +561,30 @@ 0 0 + + 3 + 10 + 1 + 0 + 0 + 0 + ..\perfc_port_default.c + perfc_port_default.c + 0 + 0 + + + 3 + 11 + 5 + 0 + 0 + 0 + ..\perfc_port_default.h + perfc_port_default.h + 0 + 0 + diff --git a/example/gcc_example.uvprojx b/example/gcc_example.uvprojx index 5ef3c7e..acf8ed4 100644 --- a/example/gcc_example.uvprojx +++ b/example/gcc_example.uvprojx @@ -403,6 +403,16 @@ 4 ..\lib\libperf_counter_gcc.a + + perfc_port_default.c + 1 + ..\perfc_port_default.c + + + perfc_port_default.h + 5 + ..\perfc_port_default.h + @@ -852,6 +862,16 @@ + + perfc_port_default.c + 1 + ..\perfc_port_default.c + + + perfc_port_default.h + 5 + ..\perfc_port_default.h + diff --git a/example/main.c b/example/main.c index 11a7cd9..fa6ce30 100644 --- a/example/main.c +++ b/example/main.c @@ -190,14 +190,25 @@ int main (void) #endif while (1) { - if (perfc_is_time_out_ms(1000)) { - printf("\r[%010d]", get_system_ms()); + if (perfc_is_time_out_ms(10000)) { + printf("\r[%010lld]", get_system_ms()); } - __cpu_time__(10) { + __cpu_usage__(10) { delay_us(30000); } - delay_us(70000); + + float fUsage = 0; + __cpu_usage__(10, { + fUsage = __usage__; + printf("task 1 cpu usage %3.2f %%\r\n", (double)fUsage); + }) { + delay_us(50000); + } + + + + delay_us(20000); } } diff --git a/gen_pack.sh b/gen_pack.sh index 4646060..3dec418 100755 --- a/gen_pack.sh +++ b/gen_pack.sh @@ -32,7 +32,7 @@ DEFAULT_ARGS=(-c "v") benchmark documents os - lib + template " # Specify file names to be added to pack base directory @@ -42,6 +42,10 @@ DEFAULT_ARGS=(-c "v") LICENSE perf_counter.c perf_counter.h + perfc_port_default.c + perfc_port_default.h + perfc_port_pmu.c + perfc_port_pmu.h README.md systick_wrapper_gcc.S systick_wrapper_gnu.s diff --git a/lib/LICENSE b/lib/LICENSE deleted file mode 100644 index 261eeb9..0000000 --- a/lib/LICENSE +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. Definitions. - - "License" shall mean the terms and conditions for use, reproduction, - and distribution as defined by Sections 1 through 9 of this document. - - "Licensor" shall mean the copyright owner or entity authorized by - the copyright owner that is granting the License. - - "Legal Entity" shall mean the union of the acting entity and all - other entities that control, are controlled by, or are under common - control with that entity. For the purposes of this definition, - "control" means (i) the power, direct or indirect, to cause the - direction or management of such entity, whether by contract or - otherwise, or (ii) ownership of fifty percent (50%) or more of the - outstanding shares, or (iii) beneficial ownership of such entity. - - "You" (or "Your") shall mean an individual or Legal Entity - exercising permissions granted by this License. - - "Source" form shall mean the preferred form for making modifications, - including but not limited to software source code, documentation - source, and configuration files. - - "Object" form shall mean any form resulting from mechanical - transformation or translation of a Source form, including but - not limited to compiled object code, generated documentation, - and conversions to other media types. - - "Work" shall mean the work of authorship, whether in Source or - Object form, made available under the License, as indicated by a - copyright notice that is included in or attached to the work - (an example is provided in the Appendix below). - - "Derivative Works" shall mean any work, whether in Source or Object - form, that is based on (or derived from) the Work and for which the - editorial revisions, annotations, elaborations, or other modifications - represent, as a whole, an original work of authorship. For the purposes - of this License, Derivative Works shall not include works that remain - separable from, or merely link (or bind by name) to the interfaces of, - the Work and Derivative Works thereof. - - "Contribution" shall mean any work of authorship, including - the original version of the Work and any modifications or additions - to that Work or Derivative Works thereof, that is intentionally - submitted to Licensor for inclusion in the Work by the copyright owner - or by an individual or Legal Entity authorized to submit on behalf of - the copyright owner. For the purposes of this definition, "submitted" - means any form of electronic, verbal, or written communication sent - to the Licensor or its representatives, including but not limited to - communication on electronic mailing lists, source code control systems, - and issue tracking systems that are managed by, or on behalf of, the - Licensor for the purpose of discussing and improving the Work, but - excluding communication that is conspicuously marked or otherwise - designated in writing by the copyright owner as "Not a Contribution." - - "Contributor" shall mean Licensor and any individual or Legal Entity - on behalf of whom a Contribution has been received by Licensor and - subsequently incorporated within the Work. - - 2. Grant of Copyright License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - copyright license to reproduce, prepare Derivative Works of, - publicly display, publicly perform, sublicense, and distribute the - Work and such Derivative Works in Source or Object form. - - 3. Grant of Patent License. Subject to the terms and conditions of - this License, each Contributor hereby grants to You a perpetual, - worldwide, non-exclusive, no-charge, royalty-free, irrevocable - (except as stated in this section) patent license to make, have made, - use, offer to sell, sell, import, and otherwise transfer the Work, - where such license applies only to those patent claims licensable - by such Contributor that are necessarily infringed by their - Contribution(s) alone or by combination of their Contribution(s) - with the Work to which such Contribution(s) was submitted. If You - institute patent litigation against any entity (including a - cross-claim or counterclaim in a lawsuit) alleging that the Work - or a Contribution incorporated within the Work constitutes direct - or contributory patent infringement, then any patent licenses - granted to You under this License for that Work shall terminate - as of the date such litigation is filed. - - 4. Redistribution. You may reproduce and distribute copies of the - Work or Derivative Works thereof in any medium, with or without - modifications, and in Source or Object form, provided that You - meet the following conditions: - - (a) You must give any other recipients of the Work or - Derivative Works a copy of this License; and - - (b) You must cause any modified files to carry prominent notices - stating that You changed the files; and - - (c) You must retain, in the Source form of any Derivative Works - that You distribute, all copyright, patent, trademark, and - attribution notices from the Source form of the Work, - excluding those notices that do not pertain to any part of - the Derivative Works; and - - (d) If the Work includes a "NOTICE" text file as part of its - distribution, then any Derivative Works that You distribute must - include a readable copy of the attribution notices contained - within such NOTICE file, excluding those notices that do not - pertain to any part of the Derivative Works, in at least one - of the following places: within a NOTICE text file distributed - as part of the Derivative Works; within the Source form or - documentation, if provided along with the Derivative Works; or, - within a display generated by the Derivative Works, if and - wherever such third-party notices normally appear. The contents - of the NOTICE file are for informational purposes only and - do not modify the License. You may add Your own attribution - notices within Derivative Works that You distribute, alongside - or as an addendum to the NOTICE text from the Work, provided - that such additional attribution notices cannot be construed - as modifying the License. - - You may add Your own copyright statement to Your modifications and - may provide additional or different license terms and conditions - for use, reproduction, or distribution of Your modifications, or - for any such Derivative Works as a whole, provided Your use, - reproduction, and distribution of the Work otherwise complies with - the conditions stated in this License. - - 5. Submission of Contributions. Unless You explicitly state otherwise, - any Contribution intentionally submitted for inclusion in the Work - by You to the Licensor shall be under the terms and conditions of - this License, without any additional terms or conditions. - Notwithstanding the above, nothing herein shall supersede or modify - the terms of any separate license agreement you may have executed - with Licensor regarding such Contributions. - - 6. Trademarks. This License does not grant permission to use the trade - names, trademarks, service marks, or product names of the Licensor, - except as required for reasonable and customary use in describing the - origin of the Work and reproducing the content of the NOTICE file. - - 7. Disclaimer of Warranty. Unless required by applicable law or - agreed to in writing, Licensor provides the Work (and each - Contributor provides its Contributions) on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or - implied, including, without limitation, any warranties or conditions - of TITLE, NON-INFRINGEMENT, MERCHANTABILITY, or FITNESS FOR A - PARTICULAR PURPOSE. You are solely responsible for determining the - appropriateness of using or redistributing the Work and assume any - risks associated with Your exercise of permissions under this License. - - 8. Limitation of Liability. In no event and under no legal theory, - whether in tort (including negligence), contract, or otherwise, - unless required by applicable law (such as deliberate and grossly - negligent acts) or agreed to in writing, shall any Contributor be - liable to You for damages, including any direct, indirect, special, - incidental, or consequential damages of any character arising as a - result of this License or out of the use or inability to use the - Work (including but not limited to damages for loss of goodwill, - work stoppage, computer failure or malfunction, or any and all - other commercial damages or losses), even if such Contributor - has been advised of the possibility of such damages. - - 9. Accepting Warranty or Additional Liability. While redistributing - the Work or Derivative Works thereof, You may choose to offer, - and charge a fee for, acceptance of support, warranty, indemnity, - or other liability obligations and/or rights consistent with this - License. However, in accepting such obligations, You may act only - on Your own behalf and on Your sole responsibility, not on behalf - of any other Contributor, and only if You agree to indemnify, - defend, and hold each Contributor harmless for any liability - incurred by, or claims asserted against, such Contributor by reason - of your accepting any such warranty or additional liability. - - END OF TERMS AND CONDITIONS - - APPENDIX: How to apply the Apache License to your work. - - To apply the Apache License to your work, attach the following - boilerplate notice, with the fields enclosed by brackets "[]" - replaced with your own identifying information. (Don't include - the brackets!) The text should be enclosed in the appropriate - comment syntax for the file format. We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright [yyyy] [name of copyright owner] - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/lib/libperf_counter_gcc.a b/lib/libperf_counter_gcc.a deleted file mode 100644 index fcf4f5a..0000000 Binary files a/lib/libperf_counter_gcc.a and /dev/null differ diff --git a/lib/perf_counter.h b/lib/perf_counter.h deleted file mode 100644 index 5d8eb0a..0000000 --- a/lib/perf_counter.h +++ /dev/null @@ -1,947 +0,0 @@ -/**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * -* * -* Licensed under the Apache License, Version 2.0 (the "License"); * -* you may not use this file except in compliance with the License. * -* You may obtain a copy of the License at * -* * -* http://www.apache.org/licenses/LICENSE-2.0 * -* * -* Unless required by applicable law or agreed to in writing, software * -* distributed under the License is distributed on an "AS IS" BASIS, * -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * -* See the License for the specific language governing permissions and * -* limitations under the License. * -* * -****************************************************************************/ - -#ifndef __PERFORMANCE_COUNTER_H__ -#define __PERFORMANCE_COUNTER_H__ - -/*============================ INCLUDES ======================================*/ -#include -#include -#include -#include "cmsis_compiler.h" - -#ifdef __cplusplus -extern "C" { -#endif -/*============================ MACROS ========================================*/ - -/*! - * \addtogroup gBasic 1 Basic - * @{ - */ -#define __PERF_COUNTER_VER_MAJOR__ 2 -#define __PERF_COUNTER_VER_MINOR__ 2 -#define __PERF_COUNTER_VER_REVISE__ 4 - -#define __PERF_COUNTER_VER_STR__ "" - -#define __PER_COUNTER_VER__ (__PERF_COUNTER_VER_MAJOR__ * 10000ul \ - +__PERF_COUNTER_VER_MINOR__ * 100ul \ - +__PERF_COUNTER_VER_REVISE__) - - -/*! @} */ - -/*! - * \addtogroup gHelper 4 Helper - * @{ - */ - -// for IAR -#undef __IS_COMPILER_IAR__ -#if defined(__IAR_SYSTEMS_ICC__) -# define __IS_COMPILER_IAR__ 1 -#endif - -// for arm compiler 5 -#undef __IS_COMPILER_ARM_COMPILER_5__ -#if ((__ARMCC_VERSION >= 5000000) && (__ARMCC_VERSION < 6000000)) -# define __IS_COMPILER_ARM_COMPILER_5__ 1 -#endif - - -//for arm compiler 6 - -#undef __IS_COMPILER_ARM_COMPILER_6__ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -# define __IS_COMPILER_ARM_COMPILER_6__ 1 -#endif -#undef __IS_COMPILER_ARM_COMPILER__ -#if defined(__IS_COMPILER_ARM_COMPILER_5__) && __IS_COMPILER_ARM_COMPILER_5__ \ -|| defined(__IS_COMPILER_ARM_COMPILER_6__) && __IS_COMPILER_ARM_COMPILER_6__ -# define __IS_COMPILER_ARM_COMPILER__ 1 -#endif - -// for clang -#undef __IS_COMPILER_LLVM__ -#if defined(__clang__) && !__IS_COMPILER_ARM_COMPILER_6__ -# define __IS_COMPILER_LLVM__ 1 -#else - -// for gcc -# undef __IS_COMPILER_GCC__ -# if defined(__GNUC__) && !( defined(__IS_COMPILER_ARM_COMPILER__) \ - || defined(__IS_COMPILER_LLVM__) \ - || defined(__IS_COMPILER_IAR__)) -# define __IS_COMPILER_GCC__ 1 -# endif - -#endif - - -#ifdef __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__ -# include __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__ -#endif - -#if defined(__clang__) -# pragma clang diagnostic push -# pragma clang diagnostic ignored "-Wunknown-warning-option" -# pragma clang diagnostic ignored "-Wreserved-identifier" -# pragma clang diagnostic ignored "-Wdeclaration-after-statement" -# pragma clang diagnostic ignored "-Wgnu-zero-variadic-macro-arguments" -# pragma clang diagnostic ignored "-Wgnu-statement-expression" -# pragma clang diagnostic ignored "-Wunused-but-set-variable" -# pragma clang diagnostic ignored "-Wshadow" -# pragma clang diagnostic ignored "-Wshorten-64-to-32" -# pragma clang diagnostic ignored "-Wcompound-token-split-by-macro" -# pragma clang diagnostic ignored "-Wunsafe-buffer-usage" -#elif defined(__IS_COMPILER_ARM_COMPILER_5__) -# pragma diag_suppress 550 -#elif defined(__IS_COMPILER_GCC__) -# pragma GCC diagnostic push -# pragma GCC diagnostic ignored "-Wpedantic" -# pragma GCC diagnostic ignored "-Wunused-variable" -# pragma GCC diagnostic ignored "-Wunused-but-set-variable" -# pragma GCC diagnostic ignored "-Wformat=" -#endif - -#ifndef __PLOOC_VA_NUM_ARGS_IMPL -# define __PLOOC_VA_NUM_ARGS_IMPL( _0,_1,_2,_3,_4,_5,_6,_7,_8,_9,_10,_11, \ - _12,_13,_14,_15,_16,__N,...) __N -#endif - -#ifndef __PLOOC_VA_NUM_ARGS -#define __PLOOC_VA_NUM_ARGS(...) \ - __PLOOC_VA_NUM_ARGS_IMPL( 0,##__VA_ARGS__,16,15,14,13,12,11,10,9, \ - 8,7,6,5,4,3,2,1,0) -#endif - -#ifndef UNUSED_PARAM -# define UNUSED_PARAM(__VAR) (void)(__VAR) -#endif - -#undef __CONNECT2 -#undef __CONNECT3 -#undef __CONNECT4 -#undef __CONNECT5 -#undef __CONNECT6 -#undef __CONNECT7 -#undef __CONNECT8 -#undef __CONNECT9 - -#undef CONNECT2 -#undef CONNECT3 -#undef CONNECT4 -#undef CONNECT5 -#undef CONNECT6 -#undef CONNECT7 -#undef CONNECT8 -#undef CONNECT9 - -#undef CONNECT - -#undef __MACRO_EXPANDING -#define __MACRO_EXPANDING(...) __VA_ARGS__ - -#define __CONNECT2(__A, __B) __A##__B -#define __CONNECT3(__A, __B, __C) __A##__B##__C -#define __CONNECT4(__A, __B, __C, __D) __A##__B##__C##__D -#define __CONNECT5(__A, __B, __C, __D, __E) __A##__B##__C##__D##__E -#define __CONNECT6(__A, __B, __C, __D, __E, __F) __A##__B##__C##__D##__E##__F -#define __CONNECT7(__A, __B, __C, __D, __E, __F, __G) \ - __A##__B##__C##__D##__E##__F##__G -#define __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \ - __A##__B##__C##__D##__E##__F##__G##__H -#define __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \ - __A##__B##__C##__D##__E##__F##__G##__H##__I - -#define ALT_CONNECT2(__A, __B) __CONNECT2(__A, __B) -#define CONNECT2(__A, __B) __CONNECT2(__A, __B) -#define CONNECT3(__A, __B, __C) __CONNECT3(__A, __B, __C) -#define CONNECT4(__A, __B, __C, __D) __CONNECT4(__A, __B, __C, __D) -#define CONNECT5(__A, __B, __C, __D, __E) __CONNECT5(__A, __B, __C, __D, __E) -#define CONNECT6(__A, __B, __C, __D, __E, __F) \ - __CONNECT6(__A, __B, __C, __D, __E, __F) -#define CONNECT7(__A, __B, __C, __D, __E, __F, __G) \ - __CONNECT7(__A, __B, __C, __D, __E, __F, __G) -#define CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) \ - __CONNECT8(__A, __B, __C, __D, __E, __F, __G, __H) -#define CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) \ - __CONNECT9(__A, __B, __C, __D, __E, __F, __G, __H, __I) - -#define CONNECT(...) \ - ALT_CONNECT2(CONNECT, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) - -#undef __using1 -#undef __using2 -#undef __using3 -#undef __using4 -#undef using - -#define __using1(__declare) \ - for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ - CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \ - ) - -#define __using2(__declare, __on_leave_expr) \ - for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ - CONNECT3(__using_, __LINE__,_ptr)++ == NULL; \ - (__on_leave_expr) \ - ) - -#define __using3(__declare, __on_enter_expr, __on_leave_expr) \ - for (__declare, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ - CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \ - ((__on_enter_expr),1) : 0; \ - (__on_leave_expr) \ - ) - -#define __using4(__dcl1, __dcl2, __on_enter_expr, __on_leave_expr) \ - for (__dcl1, __dcl2, *CONNECT3(__using_, __LINE__,_ptr) = NULL; \ - CONNECT3(__using_, __LINE__,_ptr)++ == NULL ? \ - ((__on_enter_expr),1) : 0; \ - (__on_leave_expr) \ - ) - -#define using(...) \ - CONNECT2(__using, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) - - -#undef __with2 -#undef __with3 -#undef with - -#define __with2(__type, __addr) \ - using(__type *_=(__addr)) -#define __with3(__type, __addr, __item) \ - using(__type *_=(__addr), *__item = _, _=_,_=_ ) - -#define with(...) \ - CONNECT2(__with, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) - -#undef _ - -#ifndef dimof -# define dimof(__array) (sizeof(__array)/sizeof(__array[0])) -#endif - - -#define SAFE_NAME(__NAME) CONNECT3(__,__NAME,__LINE__) - -#undef foreach2 -#undef foreach3 -#undef foreach - -#define foreach2(__type, __array) \ - using(__type *_ = __array) \ - for ( uint_fast32_t SAFE_NAME(count) = dimof(__array); \ - SAFE_NAME(count) > 0; \ - _++, SAFE_NAME(count)-- \ - ) - -#define foreach3(__type, __array, __item) \ - using(__type *_ = __array, *__item = _, _ = _, _ = _ ) \ - for ( uint_fast32_t SAFE_NAME(count) = dimof(__array); \ - SAFE_NAME(count) > 0; \ - _++, __item = _, SAFE_NAME(count)-- \ - ) - -#define foreach(...) \ - CONNECT2(foreach, __PLOOC_VA_NUM_ARGS(__VA_ARGS__))(__VA_ARGS__) - -#ifndef safe_atom_code -# define safe_atom_code() \ - using( uint32_t SAFE_NAME(temp) = \ - ({ uint32_t SAFE_NAME(temp2)=__get_PRIMASK(); \ - __disable_irq(); \ - SAFE_NAME(temp2);}), \ - __set_PRIMASK(SAFE_NAME(temp))) -#endif - -#ifndef __IRQ_SAFE -# define __IRQ_SAFE \ - using( uint32_t SAFE_NAME(temp) = \ - ({ uint32_t SAFE_NAME(temp2)=__get_PRIMASK(); \ - __disable_irq(); \ - SAFE_NAME(temp2);}), \ - __set_PRIMASK(SAFE_NAME(temp))) -#endif - -#ifndef __perf_counter_printf__ -# define __perf_counter_printf__ printf -#endif - -#if __PLOOC_VA_NUM_ARGS() != 0 -#warning Please enable GNU extensions, it is required by __cycleof__() and \ -__super_loop_monitor__() -#endif - -#if defined(__PERF_COUNTER_CFG_USE_SYSTICK_WRAPPER__) -# if defined(__IS_COMPILER_ARM_COMPILER_5__) && __IS_COMPILER_ARM_COMPILER_5__ -# pragma import(__ensure_systick_wrapper) -# elif (defined(__GNUC__) || defined(__clang__)) \ - && (!defined(__IS_COMPILER_IAR__) || !__IS_COMPILER_IAR__) -__asm(".global __ensure_systick_wrapper\n\t"); -# endif -#endif -/*! @} */ - -/*============================ MACROFIED FUNCTIONS ===========================*/ - -/*! - * \addtogroup gBasic 1 Basic - * @{ - */ - -/*! - * \brief measure the cycle count of a given code segment - * \param[in] __STR a description string for the measurement - * \param[in] ... an optional code segement, in which we can read the measured - * result from __cycle_count__. - * \details Here is an example: - E.g. - \code - __cycleof__("printf") { - printf("hello world\r\n"); - } - \endcode - */ -#define __cycleof__(__STR, ...) \ - using(int64_t _ = get_system_ticks(), __cycle_count__ = _, \ - _=_, { \ - _ = get_system_ticks() - _ - g_nOffset; \ - __cycle_count__ = _; \ - if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ - __perf_counter_printf__("\r\n"); \ - __perf_counter_printf__("-[Cycle Report]"); \ - __perf_counter_printf__( \ - "--------------------------------------------\r\n"); \ - __perf_counter_printf__( \ - __STR " total cycle count: %ld [%016lx]\r\n", \ - (long)_, (long)_); \ - } else { \ - __VA_ARGS__ \ - }; \ - }) - -/*! - * \brief measure the cpu usage for a given code segment and print out the - * result in percentage. - * \param[in] __CNT generate result on every given iterations - * \param[in] ... an optional code segement, in which we can read the measured - * result from __usage__ which is a float value. - * \details Here is an example, 50% cpu time: - E.g. - \code - while (1) { - __cpu_time__(100) { - delay_us(5000); - } - delay_us(5000); - } - \endcode - */ -#define __cpu_time__(__CNT, ...) \ - static int64_t SAFE_NAME(s_lTimestamp) = 0, SAFE_NAME(s_lTotal) = 0; \ - static uint32_t s_wLoopCounter = (__CNT); \ - using(float __usage__ = 0, ({ \ - if (0 == s_wLoopCounter) { \ - __usage__ = (float)((double)SAFE_NAME(s_lTotal) \ - / (double)( get_system_ticks() \ - - SAFE_NAME(s_lTimestamp))); \ - __usage__ *= 100.0f; \ - SAFE_NAME(s_lTimestamp) = 0; \ - SAFE_NAME(s_lTotal) = 0; \ - if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ - __perf_counter_printf__("CPU Usage %3.2f%%\r\n", (double)__usage__); \ - } else { \ - __VA_ARGS__ \ - } \ - } \ - if (0 == SAFE_NAME(s_lTimestamp)) { \ - SAFE_NAME(s_lTimestamp) = get_system_ticks(); \ - s_wLoopCounter = (__CNT); \ - } \ - start_task_cycle_counter();}), \ - ({SAFE_NAME(s_lTotal) += stop_task_cycle_counter(); \ - s_wLoopCounter--;})) - -/*! - * \addtogroup gBasicTimerService 1.2 Timer Service - * \ingroup gBasic - * @{ - */ - -/*! - * \brief should not use - */ -#define perfc_is_time_out_ms0() true - -/*! - * \brief set an alarm with given period in ms and check the status - * - * \param[in] __ms a time period in millisecond - * \param[in] __timestamp_ptr an optional timestamp holder - * \param[in] __auto_reload whether starting next period after a timeout event - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_ms3(__ms, __timestamp_ptr, __auto_reload) \ - ({ static int64_t SAFE_NAME(s_lTimestamp); (void)SAFE_NAME(s_lTimestamp); \ - __perfc_is_time_out(perfc_convert_ms_to_ticks(__ms), \ - (__timestamp_ptr), (__auto_reload));}) - -/*! - * \brief set an alarm with given period in ms and check the status - * - * \param[in] __ms a time period in millisecond - * \param[in] __timestamp_ptr an optional timestamp holder - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_ms2(__ms, __timestamp_ptr) \ - perfc_is_time_out_ms3((__ms), (__timestamp_ptr), true) - - -/*! - * \brief set an alarm with given period in ms and check the status - * - * \param[in] __ms a time period in millisecond - * \param[in] __timestamp_ptr an optional timestamp holder - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_ms1(__ms) \ - perfc_is_time_out_ms3((__ms), &SAFE_NAME(s_lTimestamp), true) - -/*! - * \brief set an alarm with given period in ms and check the status - * - * \param[in] __ms a time period in millisecond - * \param[in] ... an optional timestamp holder - * \param[in] ... an optional indicator for whether starting next period after a timeout event - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_ms(...) \ - CONNECT2(perfc_is_time_out_ms, __PLOOC_VA_NUM_ARGS(__VA_ARGS__)) \ - (__VA_ARGS__) - -/*! - * \brief set an alarm with given period in us and check the status - * - * \param[in] __us a time period in microsecond - * \param[in] __timestamp_ptr an optional timestamp holder - * \param[in] __auto_reload whether starting next period after a timeout event - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_us3(__us, __timestamp_ptr, __auto_reload) \ - ({ static int64_t SAFE_NAME(s_lTimestamp); (void)SAFE_NAME(s_lTimestamp); \ - __perfc_is_time_out(perfc_convert_us_to_ticks(__us), \ - (__timestamp_ptr), (__auto_reload));}) - -/*! - * \brief set an alarm with given period in us and check the status - * - * \param[in] __us a time period in microsecond - * \param[in] __timestamp_ptr an optional timestamp holder - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_us2(__us, __timestamp_ptr) \ - perfc_is_time_out_us3((__us), (__timestamp_ptr), true) - - -/*! - * \brief set an alarm with given period in us and check the status - * - * \param[in] __us a time period in microsecond - * \param[in] __timestamp_ptr an optional timestamp holder - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_us1(__us) \ - perfc_is_time_out_us3((__us), &SAFE_NAME(s_lTimestamp), true) - -/*! - * \brief set an alarm with given period in us and check the status - * - * \param[in] __us a time period in microsecond - * \param[in] ... an optional timestamp holder - * \param[in] ... an optional indicator for whether starting next period after a timeout event - * - * \return bool whether it is timeout - */ -#define perfc_is_time_out_us(...) \ - CONNECT2(perfc_is_time_out_us, __PLOOC_VA_NUM_ARGS(__VA_ARGS__)) \ - (__VA_ARGS__) - - -/*! @} */ - -/*! @} */ - -/*! - * \addtogroup gRTOS 2 RTOS Support - * @{ - */ -#define __super_loop_monitor__(__N, ...) \ - using( \ - struct { \ - int64_t lStart; \ - int64_t lTaskUsedCycles; \ - int64_t lTimeElapsed; \ - } __cpu_usage__ = {.lStart = get_system_ticks()}) \ - using(int SAFE_NAME(cnt) = (__N)) \ - for(start_task_cycle_counter();; ({ \ - if (!(--SAFE_NAME(cnt))) { \ - __cpu_usage__.lTimeElapsed \ - = get_system_ticks() - __cpu_usage__.lStart - g_nOffset; \ - __cpu_usage__.lTaskUsedCycles = stop_task_cycle_counter(); \ - \ - if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ - __perf_counter_printf__( \ - "%s CPU Usage %2.3f%%\r\n", __func__, \ - (float)((double)__cpu_usage__.lTaskUsedCycles * 100.0 / \ - (double)__cpu_usage__.lTimeElapsed)); \ - } else { \ - __VA_ARGS__; \ - } \ - SAFE_NAME(cnt) = (__N); \ - __cpu_usage__.lStart = get_system_ticks(); \ - start_task_cycle_counter(); \ - }; \ - })) - -/*============================ TYPES =========================================*/ -typedef struct { - int64_t lStart; - int64_t lUsedTotal; - int32_t nUsedRecent; - uint16_t hwActiveCount; - uint16_t : 15; - uint16_t bEnabled : 1; -} task_cycle_info_t; - -typedef struct task_cycle_info_agent_t task_cycle_info_agent_t; - -struct task_cycle_info_agent_t { - task_cycle_info_t *ptInfo; - task_cycle_info_agent_t *ptNext; - task_cycle_info_agent_t *ptPrev; -}; - -/*! @} */ - -/*============================ GLOBAL VARIABLES ==============================*/ -extern volatile int64_t g_lLastTimeStamp; -extern volatile int32_t g_nOffset; -/*============================ LOCAL VARIABLES ===============================*/ -/*============================ PROTOTYPES ====================================*/ - - - -/*! - * \addtogroup gBasicTicks 1.1 Ticks APIs - * \ingroup gBasic - * @{ - */ -/*! - * \brief get the elapsed cycles since perf_counter is initialised - * \return int64_t the elpased cycles - */ -__attribute__((noinline)) -extern int64_t get_system_ticks(void); - - -#ifdef __PERF_CNT_USE_LONG_CLOCK__ -/*! \note the prototype of this clock() is different from the one defined in - *! time.h. As clock_t is usually defined as unsigned int, it is - *! not big enough in Cortex-M system to hold a time-stamp. clock() - *! defined here returns the timestamp since the begining of main() - *! and its unit is clock cycle (rather than 1ms). Hence, for a system - *! running under several hundreds MHz or even 1GHz, e.g. RT10xx from - *! NXP, it is very easy to see a counter overflow as clock_t is - *! defined as uint32_t in timer.h. - *! Since we are not allowed to change the defintion of clock_t in - *! official header file, i.e. time.h, I use a compatible prototype - *! after I checked the AAPCS spec. So, the return of the clock() is - *! int64_t, which will use the R0 to store the lower 32bits and R1 - *! to store the higher 32bits. When you are using the prototype from - *! timer.h, caller will only take the lower 32bits stored in R0 and - *! the higher 32bits stored in R1 will be ignored. - *! - *! If you want to use the non-overflow version of this clock(), please - *! 1) define the MACRO: __PERF_CNT_USE_LONG_CLOCK__ in your project - *! and 2) do not include system header file - *! - */ -#if !defined(__IS_COMPILER_IAR__) -__attribute__((nothrow)) -#endif -__attribute__((noinline)) -extern int64_t clock(void); -#endif - -/*! - * \brief try to set a start pointer for the performance counter - */ -__STATIC_INLINE -void start_cycle_counter(void) -{ - g_lLastTimeStamp = get_system_ticks(); -} - -/*! - * \brief calculate the elapsed cycle count since the last start point - * \note you can have multiple stop_cycle_counter following one start point - * \return int32_t the elapsed cycle count - */ -__STATIC_INLINE -int64_t stop_cycle_counter(void) -{ - int64_t lTemp = (get_system_ticks() - g_lLastTimeStamp); - - return lTemp - g_nOffset; -} - - - - -/*! @} */ - - -/*! - * \addtogroup gBasicTimerService 1.2 Timer Service - * \ingroup gBasic - * @{ - */ - -/*! - * \brief get the elapsed milliseconds since perf_counter is initialised - * \return int32_t the elapsed milliseconds - */ -extern int32_t get_system_ms(void); - -/*! - * \brief get the elapsed microsecond since perf_counter is initialised - * \return int32_t the elapsed microsecond - */ -extern int32_t get_system_us(void); - - - -/*! - * \brief delay specified time in microsecond - * \param[in] nUs time in microsecond - */ -extern void delay_us(int32_t nUs); - -/*! - * \brief delay specified time in millisecond - * \param[in] nMs time in millisecond - */ -extern void delay_ms(int32_t nMs); - -/*! - * \brief convert ticks of a reference timer to millisecond - * - * \param[in] lTick the tick count - * \return int64_t the millisecond - */ -extern -int64_t perfc_convert_ticks_to_ms(int64_t lTick); - -/*! - * \brief convert millisecond into ticks of the reference timer - * - * \param[in] wMS the target time in millisecond - * \return int64_t the ticks - */ -extern -int64_t perfc_convert_ms_to_ticks(uint32_t wMS); - -/*! - * \brief convert ticks of a reference timer to microsecond - * - * \param[in] lTick the tick count - * \return int64_t the microsecond - */ -extern -int64_t perfc_convert_ticks_to_us(int64_t lTick); - -/*! - * \brief convert microsecond into ticks of the reference timer - * - * \param[in] wUS the target time in microsecond - * \return int64_t the ticks - */ -extern -int64_t perfc_convert_us_to_ticks(uint32_t wUS); - -/*! - * \brief set an alarm with given period and check the status - * - * \param[in] lPeriod a time period in ticks - * \param[in] plTimestamp a pointer points to an int64_t integer, if NULL is - * passed, an static local variable inside the function will be used - * \param[in] bAutoReload whether starting next period after a timeout event. - * \return bool whether it is timeout or not - */ -extern -bool __perfc_is_time_out(int64_t lPeriod, int64_t *plTimestamp, bool bAutoReload); - -/*! @} */ - - - - -/*! - * \addtogroup gRTOS 2 RTOS Support - * @{ - */ - -#if defined(__PERF_CNT_USE_RTOS__) - -/*! \brief initialize the default virtual cycle counter for the current task - */ -extern void init_task_cycle_counter(void); - -/*! \brief check whether the task stack canary is safe or not - * \retval false likely to be a stack-overflow - * \retval true task stack is safe - */ -extern -bool perfc_check_task_stack_canary_safe(void); - -/*! \brief provide cycle information for target task - * \details Support RTOS List: - * - RTX5 - * - RT-Thread - * - ThreadX - * - FreeRTOS - * - * \return task_cycle_info_t* the cycle info object passed to this function - */ -extern task_cycle_info_t * get_rtos_task_cycle_info(void); - - -/*! - * \brief intialize a given task_cycle_info_t object and enable it before - * registering it. - * \return task_cycle_info_t* the cycle info object passed to this function - */ -extern task_cycle_info_t *init_task_cycle_info(task_cycle_info_t *ptInfo); - -/*! \brief enable a given task_cycle_info_t object - * - * \param[in] ptInfo the address of target task_cycle_info_t object - * \return bool previous status - */ -extern bool enable_task_cycle_info(task_cycle_info_t *ptInfo); - -/*! \brief disable a given task_cycle_info_t object - * - * \param[in] ptInfo the address of target task_cycle_info_t object - * \return bool previous status - */ -extern bool disable_task_cycle_info(task_cycle_info_t *ptInfo); - -/*! \brief resume the enabled status of a given task_cycle_info_t object - * - * \param[in] ptInfo the address of target task_cycle_info_t object - * \param[in] bEnabledStatus the previous status - */ -extern -void resume_task_cycle_info(task_cycle_info_t *ptInfo, bool bEnabledStatus); - -/*! - * \brief register a global virtual cycle counter agent to the current task - * \param[in] ptInfo the address of target task_cycle_info_t object - * \param[in] ptAgent an list node for the task_cycle_info_t object - * \note the ptAgent it is better to be allocated as a static variable, global - * variable or comes from heap or pool - * - * \return task_cycle_info_agent_t* the agent passed to this function - */ -extern -task_cycle_info_agent_t *register_task_cycle_agent( - task_cycle_info_t *ptInfo, - task_cycle_info_agent_t *ptAgent); - -/*! - * \brief remove a global virtual cycle counter agent from the current task - * \param[in] ptAgent the list node currently in use - * \return task_cycle_info_agent_t* the agent passed to this function - */ -extern -task_cycle_info_agent_t * -unregister_task_cycle_agent(task_cycle_info_agent_t *ptAgent); - -/*! \brief reset and start the virtual cycle counter for the current task - * - * \param[in] ptInfo the target task_cycle_info_t object - */ -__attribute__((noinline)) -extern void __start_task_cycle_counter(task_cycle_info_t *ptInfo); - -/*! \brief calculate the elapsed cycle count for current task since the last - * start point - * - * \note you can call stop_cycle_counter() multiple times following one - * start_task_cycle_counter() - * - * \param[in] ptInfo the target task_cycle_info_t object - * - * \note When ptInfo is NULL, it returns current task cycle info, when ptInfo - * is non-NULL, it returns the total used cycles of the specified - * task_cycle_info_t object. - * - * \return int64_t the elapsed cycle count. - */ -__attribute__((noinline)) -extern int64_t __stop_task_cycle_counter(task_cycle_info_t *ptInfo); - - -#define start_task_cycle_counter(...) \ - __start_task_cycle_counter((NULL,##__VA_ARGS__)) - -#define stop_task_cycle_counter(...) \ - __stop_task_cycle_counter((NULL,##__VA_ARGS__)) - -#elif !defined(__IMPLEMENT_PERF_COUNTER) -# define start_task_cycle_counter(...) start_cycle_counter() -# define stop_task_cycle_counter(...) stop_cycle_counter() -# define init_task_cycle_counter() -# define register_task_cycle_agent(...) -# define unregister_task_cycle_agent(...) -# define init_task_cycle_info(...) (NULL) -# define enable_task_cycle_info(...) (false) -# define disable_task_cycle_info(...) (false) -# define resume_task_cycle_info(...) -# define perfc_check_task_stack_canary_safe() (false) -#endif - -/*! @} */ - -/*! - * \addtogroup gBasic 1 Basic - * @{ - */ - -/*----------------------------------------------------------------------------* - * Please ignore the following APIs unless you have encountered some known * - * special conditions * - *----------------------------------------------------------------------------*/ - -/*! \brief initialise cycle counter service - * \note - don't forget to tell the function whether the systick is already - * used by user applications. - * Don't worry, this cycle counter service won't affect your existing - * systick service. - * - * \note - Usually the perf_counter can initialise itself with the help of - * __attribute__((constructor(255))), this works fine in Arm Compiler - * 5 (armcc), Arm Compiler 6 (armclang), arm gcc and llvm. It doesn't - * work for IAR. So, when you are using IAR, please call this function - * manually to initialise the perf_counter service. - * - * \note - Perf_counter library assumes that: - * 1. Your project has already using SysTick - * 2. It assumes that you have already implemented the SysTick_Handler - * 3. It assumes that you have enabled the exception handling for - * SysTick. - * If these are not the case, please: - * 1. Add an empty SysTick_Handler to your project if you don't have - * one - * 2. Make sure you have the SysTick Exception handling enabled - * 3. And call function init_cycle_counter(false) if you doesn't - * use SysTick in your project at all. - * - * \param[in] bIsSysTickOccupied A boolean value which indicates whether SysTick - * is already used by user application. - */ -extern void init_cycle_counter(bool bIsSysTickOccupied); - - -/*! - * \brief a system timer handler inserted to the SysTick_Handler - * - * \note - if you are using a compiler other than armcc or armclang, e.g. iar, - * arm gcc etc, the systick_wrapper_ual.o doesn't work with the linker - * of your target toolchain as it use the $Super$$ which is only supported - * by armlink. For this condition, you have to manually put this function - * into your existing SysTick_Handler to make the perf_counter library - * work. - * - * \note - if you are using Arm Compiler 5 (armcc) or Arm Compiler 6 (armclang) - * you do NOT have to insert this function into your SysTick_Handler, - * the systick_wrapper_ual.s will do the work for you. - */ -extern void user_code_insert_to_systick_handler(void); - -/*! - * \brief update perf_counter as SystemCoreClock has been updated. - */ -extern void update_perf_counter(void); - -/*! - * \brief prepare for reconfiguration of SysTick timer. - * - * \note some systems (e.g. FreeRTOS) might reconfigure the systick timer to - * fulfil the requirement of their feature. To support this, just - * before the reconfiguration, please call this function in order - * to make the perf_counter works correctly later. - * - * \note after the reconfiguration, please call update_perf_counter() to apply - * the changes to perf_counter. - * - * \note this function will stop the SysTick, clear the pending bit and set - * the Load register and Current Value register to zero. - */ -extern void before_cycle_counter_reconfiguration(void); - -/*! @} */ - -/*! - * \addtogroup gBenchmark 3 Benchmark - * @{ - */ - -#ifdef __PERF_COUNTER_COREMARK__ - -/*! - * \brief entry for coremark - */ -void coremark_main(void); -#endif - -/*! @} */ - - -//#if defined(__clang__) -//# pragma clang diagnostic pop -//#elif defined(__IS_COMPILER_GCC__) -//# pragma GCC diagnostic pop -//#endif - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/lib/perf_counter.lib b/lib/perf_counter.lib deleted file mode 100644 index dcbd912..0000000 Binary files a/lib/perf_counter.lib and /dev/null differ diff --git a/lib/perf_os_patch_freertos.c b/lib/perf_os_patch_freertos.c deleted file mode 100644 index 164a6c6..0000000 --- a/lib/perf_os_patch_freertos.c +++ /dev/null @@ -1,240 +0,0 @@ -/**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * -* * -* Licensed under the Apache License, Version 2.0 (the "License"); * -* you may not use this file except in compliance with the License. * -* You may obtain a copy of the License at * -* * -* http://www.apache.org/licenses/LICENSE-2.0 * -* * -* Unless required by applicable law or agreed to in writing, software * -* distributed under the License is distributed on an "AS IS" BASIS, * -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * -* See the License for the specific language governing permissions and * -* limitations under the License. * -* * -****************************************************************************/ - - -/*============================ INCLUDES ======================================*/ - - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "stack_macros.h" - -/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified -because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined -for the header files above, but not in this file, in order to generate the -correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */ - -#include "perf_counter.h" -#include "cmsis_compiler.h" - -/*============================ MACROS ========================================*/ - -#undef __WRAP_FUNC -#undef WRAP_FUNC -#if defined(__IS_COMPILER_ARM_COMPILER__) && __IS_COMPILER_ARM_COMPILER__ - -# define __WRAP_FUNC(__NAME) $Sub$$##__NAME -# define __ORIG_FUNC(__NAME) $Super$$##__NAME - -#elif (defined(__IS_COMPILER_LLVM__) && __IS_COMPILER_LLVM__) \ - || (defined(__IS_COMPILER_GCC__) && __IS_COMPILER_GCC__) - -# define __WRAP_FUNC(__NAME) __wrap_##__NAME -# define __ORIG_FUNC(__NAME) __real_##__NAME - -#endif -#define WRAP_FUNC(__NAME) __WRAP_FUNC(__NAME) -#define ORIG_FUNC(__NAME) __ORIG_FUNC(__NAME) - -struct __task_cycle_info_t { - task_cycle_info_t tInfo; - int64_t lLastTimeStamp; - task_cycle_info_agent_t tList; - uint32_t wMagicWord; -} ; - - - -/*============================ TYPES =========================================*/ - -/* - * Task control block. A task control block (TCB) is allocated for each task, - * and stores task state information, including a pointer to the task's context - * (the task's run time environment, including register values) - */ -typedef struct tskTaskControlBlock /* The old naming convention is used to prevent breaking kernel aware debuggers. */ -{ - volatile StackType_t *pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack. THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */ - - #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer. THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */ - #endif - - ListItem_t xStateListItem; /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */ - ListItem_t xEventListItem; /*< Used to reference a task from an event list. */ - UBaseType_t uxPriority; /*< The priority of the task. 0 is the lowest priority. */ - StackType_t *pxStack; /*< Points to the start of the stack. */ - char pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created. Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */ - - #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - StackType_t *pxEndOfStack; /*< Points to the highest valid address for the stack. */ - #endif - - #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */ - #endif - - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxTCBNumber; /*< Stores a number that increments each time a TCB is created. It allows debuggers to determine when a task has been deleted and then recreated. */ - UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */ - #endif - - #if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */ - UBaseType_t uxMutexesHeld; - #endif - - #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - TaskHookFunction_t pxTaskTag; - #endif - - #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) - void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; - #endif - - #if( configGENERATE_RUN_TIME_STATS == 1 ) - uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */ - #endif - - #if ( configUSE_NEWLIB_REENTRANT == 1 ) - /* Allocate a Newlib reent structure that is specific to this task. - Note Newlib support has been included by popular demand, but is not - used by the FreeRTOS maintainers themselves. FreeRTOS is not - responsible for resulting newlib operation. User must be familiar with - newlib and must provide system-wide implementations of the necessary - stubs. Be warned that (at the time of writing) the current newlib design - implements a system-wide malloc() that must be provided with locks. - - See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html - for additional information. */ - struct _reent xNewLib_reent; - #endif - - #if( configUSE_TASK_NOTIFICATIONS == 1 ) - volatile uint32_t ulNotifiedValue; - volatile uint8_t ucNotifyState; - #endif - - /* See the comments in FreeRTOS.h with the definition of - tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */ - #if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */ - uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */ - #endif - - #if( INCLUDE_xTaskAbortDelay == 1 ) - uint8_t ucDelayAborted; - #endif - - #if( configUSE_POSIX_ERRNO == 1 ) - int iTaskErrno; - #endif - -} tskTCB; - -/* The old tskTCB name is maintained above then typedefed to the new TCB_t name -below to enable the use of older kernel aware debuggers. */ -typedef tskTCB TCB_t; - -/*lint -save -e956 A manual analysis and inspection has been used to determine -which static variables must be declared volatile. */ -PRIVILEGED_DATA -extern TCB_t * volatile pxCurrentTCB; - -/*! \note if you aren't using perf_counter inside KEIL with RTE, please create - *! a header file called "Pre_Include_Global.h", copy the following - *! content into the header file and and put following option - *! to your command line (supposing you are using arm compiler 6): - *! -include "Pre_Include_Global.h" - */ - -/* -//! \brief Enable RTOS Patch for perf_counter -#define __PERF_CNT_USE_RTOS__ - -#define traceTASK_SWITCHED_OUT_DISABLE -#define traceTASK_SWITCHED_IN_DISABLE - -extern void __freertos_evr_on_task_switched_out (void *ptTCB); -extern void __freertos_evr_on_task_switched_in(void *ptTCB, unsigned int uxTopPriority) ; - -# define traceTASK_SWITCHED_OUT() \ - __freertos_evr_on_task_switched_out(pxCurrentTCB) -# define traceTASK_SWITCHED_IN() \ - __freertos_evr_on_task_switched_in(pxCurrentTCB, uxTopReadyPriority) - - */ - - -/*============================ GLOBAL VARIABLES ==============================*/ -/*============================ LOCAL VARIABLES ===============================*/ -/*============================ PROTOTYPES ====================================*/ -extern void __on_context_switch_in(uint32_t *pwStack); -extern void __on_context_switch_out(uint32_t *pwStack); - -/*============================ IMPLEMENTATION ================================*/ - - -#if defined(RTE_Compiler_EventRecorder) - -# include "EventRecorder.h" - -#endif - - -#define EvtFreeRTOSTasksNo (0xF0U) - -#define EvtFreeRTOSTasks_TaskSwitchedOut \ - EventID(EventLevelOp, EvtFreeRTOSTasksNo, 0x0BU) -#define EvtFreeRTOSTasks_TaskSwitchedIn \ - EventID(EventLevelOp, EvtFreeRTOSTasksNo, 0x0CU) - -void __freertos_evr_on_task_switched_out (void *ptTCB) { -#if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtFreeRTOSTasks_TaskSwitchedOut, (uint32_t)ptTCB, 0U); -#else - (void)pxCurrentTCB; -#endif - - __on_context_switch_out(((TCB_t *)ptTCB)->pxStack); - -} - - -void __freertos_evr_on_task_switched_in(void *ptTCB, uint32_t uxTopPriority) { -#if defined(RTE_Compiler_EventRecorder) - EventRecord2(EvtFreeRTOSTasks_TaskSwitchedIn, (uint32_t)ptTCB, uxTopPriority); -#else - (void)pxCurrentTCB; - (void)uxTopPriority; -#endif - - __on_context_switch_in(((TCB_t *)ptTCB)->pxStack); -} - - -task_cycle_info_t * get_rtos_task_cycle_info(void) -{ - return &(((struct __task_cycle_info_t *)pxCurrentTCB->pxStack)->tInfo); -} diff --git a/lib/perf_os_patch_rt_thread.c b/lib/perf_os_patch_rt_thread.c deleted file mode 100644 index c5fecd9..0000000 --- a/lib/perf_os_patch_rt_thread.c +++ /dev/null @@ -1,112 +0,0 @@ -/**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * -* * -* Licensed under the Apache License, Version 2.0 (the "License"); * -* you may not use this file except in compliance with the License. * -* You may obtain a copy of the License at * -* * -* http://www.apache.org/licenses/LICENSE-2.0 * -* * -* Unless required by applicable law or agreed to in writing, software * -* distributed under the License is distributed on an "AS IS" BASIS, * -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * -* See the License for the specific language governing permissions and * -* limitations under the License. * -* * -****************************************************************************/ - - -/*============================ INCLUDES ======================================*/ - - -#include -#include "perf_counter.h" -#include "cmsis_compiler.h" - -/*============================ MACROS ========================================*/ - -#undef __WRAP_FUNC -#undef WRAP_FUNC -#if defined(__IS_COMPILER_ARM_COMPILER__) && __IS_COMPILER_ARM_COMPILER__ - -# define __WRAP_FUNC(__NAME) $Sub$$##__NAME -# define __ORIG_FUNC(__NAME) $Super$$##__NAME - -#elif (defined(__IS_COMPILER_LLVM__) && __IS_COMPILER_LLVM__) \ - || (defined(__IS_COMPILER_GCC__) && __IS_COMPILER_GCC__) - -# define __WRAP_FUNC(__NAME) __wrap_##__NAME -# define __ORIG_FUNC(__NAME) __real_##__NAME - -#endif -#define WRAP_FUNC(__NAME) __WRAP_FUNC(__NAME) -#define ORIG_FUNC(__NAME) __ORIG_FUNC(__NAME) - -struct __task_cycle_info_t { - task_cycle_info_t tInfo; - int64_t lLastTimeStamp; - task_cycle_info_agent_t tList; - uint32_t wMagicWord; -} ; - -#ifndef RT_USING_HOOK -#error "In order to use perf_counter:RT-Thread-Patch, please define RT_USING_HOOK \ -in rtconfig.h. If you don't want to use this patch, please un-select it in RTE." -#endif - - -/*============================ TYPES =========================================*/ -/*============================ GLOBAL VARIABLES ==============================*/ -/*============================ LOCAL VARIABLES ===============================*/ -/*============================ PROTOTYPES ====================================*/ -extern void __on_context_switch_in(uint32_t *pwStack); -extern void __on_context_switch_out(uint32_t *pwStack); -extern struct rt_thread *rt_current_thread; -/*============================ IMPLEMENTATION ================================*/ - -void __rt_thread_scheduler_hook(struct rt_thread *from, struct rt_thread *to) -{ - if (NULL != from) { - __on_context_switch_out(from->stack_addr); - } - - __on_context_switch_in(to->stack_addr); -} - -task_cycle_info_t * get_rtos_task_cycle_info(void) -{ - return &(((struct __task_cycle_info_t *)rt_current_thread->stack_addr)->tInfo); -} - -void __perf_os_patch_init(void) -{ -#if defined(RTTHREAD_VERSION) && (RTTHREAD_VERSION >= (4 * 10000)) - rt_tick_sethook(user_code_insert_to_systick_handler); -#endif - -#if !defined(PKG_USING_PERF_COUNTER) || (defined(PKG_PERF_COUNTER_USING_THREAD_STATISTIC)) - rt_scheduler_sethook(__rt_thread_scheduler_hook); -#endif -} - -#ifdef PKG_USING_PERF_COUNTER - -#if defined(RTTHREAD_VERSION) && (RTTHREAD_VERSION >= (4 * 10000)) -void __ensure_systick_wrapper(void) -{ -} -#endif - -#define DBG_TAG "perf_counter" -#define DBG_LVL DBG_INFO -#include - -static int _perf_counter_init(void) -{ - extern uint32_t SystemCoreClock; - init_cycle_counter(true); - LOG_I("perf_counter init, SystemCoreClock:%d", SystemCoreClock); - return 0; -} -INIT_PREV_EXPORT(_perf_counter_init); -#endif /* PKG_USING_PERF_COUNTER */ diff --git a/lib/perf_os_patch_rtx5.c b/lib/perf_os_patch_rtx5.c deleted file mode 100644 index 24132c7..0000000 --- a/lib/perf_os_patch_rtx5.c +++ /dev/null @@ -1,99 +0,0 @@ -/**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * -* * -* Licensed under the Apache License, Version 2.0 (the "License"); * -* you may not use this file except in compliance with the License. * -* You may obtain a copy of the License at * -* * -* http://www.apache.org/licenses/LICENSE-2.0 * -* * -* Unless required by applicable law or agreed to in writing, software * -* distributed under the License is distributed on an "AS IS" BASIS, * -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * -* See the License for the specific language governing permissions and * -* limitations under the License. * -* * -****************************************************************************/ - - -/*============================ INCLUDES ======================================*/ - - -#include "rtx_os.h" -#include "perf_counter.h" -#include "cmsis_compiler.h" -#include "rtx_evr.h" // RTX Event Recorder definitions - -/*============================ MACROS ========================================*/ - -#undef __WRAP_FUNC -#undef WRAP_FUNC -#if defined(__IS_COMPILER_ARM_COMPILER__) && __IS_COMPILER_ARM_COMPILER__ - -# define __WRAP_FUNC(__NAME) $Sub$$##__NAME -# define __ORIG_FUNC(__NAME) $Super$$##__NAME - -#elif (defined(__IS_COMPILER_LLVM__) && __IS_COMPILER_LLVM__) \ - || (defined(__IS_COMPILER_GCC__) && __IS_COMPILER_GCC__) - -# define __WRAP_FUNC(__NAME) __wrap_##__NAME -# define __ORIG_FUNC(__NAME) __real_##__NAME - -#endif -#define WRAP_FUNC(__NAME) __WRAP_FUNC(__NAME) -#define ORIG_FUNC(__NAME) __ORIG_FUNC(__NAME) - -struct __task_cycle_info_t { - task_cycle_info_t tInfo; - int64_t lLastTimeStamp; - task_cycle_info_agent_t tList; - uint32_t wMagicWord; -} ; - - -/*============================ TYPES =========================================*/ -/*============================ GLOBAL VARIABLES ==============================*/ -/*============================ LOCAL VARIABLES ===============================*/ -/*============================ PROTOTYPES ====================================*/ -extern void __on_context_switch_in(uint32_t *pwStack); -extern void __on_context_switch_out(uint32_t *pwStack); - -/*============================ IMPLEMENTATION ================================*/ - - -/*! \brief wrapper function for rtos context switching */ -void __on_context_switch (osRtxThread_t *thread) -{ - if (NULL != osRtxInfo.thread.run.curr) { - __on_context_switch_out(osRtxInfo.thread.run.curr->stack_mem); - } - - __on_context_switch_in(thread->stack_mem); -} - -__attribute__((used)) -void EvrRtxThreadSwitched (osThreadId_t thread_id) -{ - __on_context_switch((osRtxThread_t *)thread_id); - -#if defined(RTE_Compiler_EventRecorder) -# define EvtRtxThreadSwitched \ - EventID(EventLevelOp, EvtRtxThreadNo, 0x19U) - - (void)EventRecord2(EvtRtxThreadSwitched, (uint32_t)thread_id, 0U); -#else - (void)thread_id; -#endif -} - - -task_cycle_info_t * get_rtos_task_cycle_info(void) -{ - osRtxThread_t *curr = osRtxInfo.thread.run.curr; - if (NULL == curr) { - return NULL; - } - - return &(((struct __task_cycle_info_t *)curr->stack_mem)->tInfo); -} - diff --git a/lib/perf_os_patch_threadx.c b/lib/perf_os_patch_threadx.c deleted file mode 100644 index dcb694e..0000000 --- a/lib/perf_os_patch_threadx.c +++ /dev/null @@ -1,128 +0,0 @@ -/**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * -* * -* Licensed under the Apache License, Version 2.0 (the "License"); * -* you may not use this file except in compliance with the License. * -* You may obtain a copy of the License at * -* * -* http://www.apache.org/licenses/LICENSE-2.0 * -* * -* Unless required by applicable law or agreed to in writing, software * -* distributed under the License is distributed on an "AS IS" BASIS, * -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * -* See the License for the specific language governing permissions and * -* limitations under the License. * -* * -****************************************************************************/ - - -/*============================ INCLUDES ======================================*/ - -#include "tx_api.h" -#include "tx_thread.h" - -#include "perf_counter.h" -#include "cmsis_compiler.h" - -/*============================ MACROS ========================================*/ - -#undef __WRAP_FUNC -#undef WRAP_FUNC -#if defined(__IS_COMPILER_ARM_COMPILER__) && __IS_COMPILER_ARM_COMPILER__ - -# define __WRAP_FUNC(__NAME) $Sub$$##__NAME -# define __ORIG_FUNC(__NAME) $Super$$##__NAME - -#elif (defined(__IS_COMPILER_LLVM__) && __IS_COMPILER_LLVM__) \ - || (defined(__IS_COMPILER_GCC__) && __IS_COMPILER_GCC__) - -# define __WRAP_FUNC(__NAME) __wrap_##__NAME -# define __ORIG_FUNC(__NAME) __real_##__NAME - -#endif -#define WRAP_FUNC(__NAME) __WRAP_FUNC(__NAME) -#define ORIG_FUNC(__NAME) __ORIG_FUNC(__NAME) - - -#if defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) && defined(TX_EXECUTION_PROFILE_ENABLE) -#error In order to use perf_counter:ThreadX-Patch, please define \ - TX_ENABLE_EXECUTION_CHANGE_NOTIFY or TX_EXECUTION_PROFILE_ENABLE \ - in the project configuration, according to the version of thread.\ - If you don't want to use this patch, please un-select it in RTE\ - or remove this patch from the compilation. -#endif - - -/*============================ TYPES =========================================*/ -struct __task_cycle_info_t { - task_cycle_info_t tInfo; - int64_t lLastTimeStamp; - task_cycle_info_agent_t tList; - uint32_t wMagicWord; -} ; - - -/*============================ GLOBAL VARIABLES ==============================*/ -/*============================ LOCAL VARIABLES ===============================*/ -/*============================ PROTOTYPES ====================================*/ -extern void __on_context_switch_in(uint32_t *pwStack); -extern void __on_context_switch_out(uint32_t *pwStack); - -/*============================ IMPLEMENTATION ================================*/ - -#if defined(TX_EXECUTION_PROFILE_ENABLE) -void WRAP_FUNC(_tx_execution_thread_enter)(void) -#else -void _tx_execution_thread_enter (void) -#endif -{ - TX_THREAD * ptThread = NULL; - TX_THREAD_GET_CURRENT(ptThread); - - __on_context_switch_in(ptThread->tx_thread_stack_start); - -#if defined(TX_EXECUTION_PROFILE_ENABLE) - extern void ORIG_FUNC(_tx_execution_thread_enter)(void); - - ORIG_FUNC(_tx_execution_thread_enter)(); -#endif -} - -#if defined(TX_EXECUTION_PROFILE_ENABLE) -void WRAP_FUNC(_tx_execution_thread_exit)(void) -#else -void _tx_execution_thread_exit(void) -#endif -{ - TX_THREAD * ptThread = NULL; - TX_THREAD_GET_CURRENT(ptThread); - - if (NULL != ptThread) { - __on_context_switch_out(ptThread->tx_thread_stack_start); - } -#if defined(TX_EXECUTION_PROFILE_ENABLE) - extern void ORIG_FUNC(_tx_execution_thread_exit)(void); - - ORIG_FUNC(_tx_execution_thread_exit)(); -#endif -} - -#if !defined(TX_EXECUTION_PROFILE_ENABLE) -void _tx_execution_isr_exit(void) -{ - -} - -void _tx_execution_isr_enter(void) -{ - -} -#endif - -task_cycle_info_t * get_rtos_task_cycle_info(void) -{ - TX_THREAD * ptThread = NULL; - TX_THREAD_GET_CURRENT(ptThread); - - return &(((struct __task_cycle_info_t *)ptThread->tx_thread_stack_start)->tInfo); -} diff --git a/os/perf_os_patch_rtx5.c b/os/perf_os_patch_rtx5.c index 24132c7..ce16b1e 100644 --- a/os/perf_os_patch_rtx5.c +++ b/os/perf_os_patch_rtx5.c @@ -76,7 +76,7 @@ void EvrRtxThreadSwitched (osThreadId_t thread_id) { __on_context_switch((osRtxThread_t *)thread_id); -#if defined(RTE_Compiler_EventRecorder) +#if defined(RTE_Compiler_EventRecorder) || defined(RTE_CMSIS_View_EventRecorder) # define EvtRtxThreadSwitched \ EventID(EventLevelOp, EvtRtxThreadNo, 0x19U) diff --git a/perf_counter.c b/perf_counter.c index 31bc2e8..5a4ccb8 100644 --- a/perf_counter.c +++ b/perf_counter.c @@ -1,5 +1,5 @@ /**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * @@ -48,114 +48,12 @@ # define PERF_CNT_DELAY_US_COMPENSATION 90 #endif - -/* IO definitions (access restrictions to peripheral registers) */ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - - #define MAGIC_WORD_AGENT_LIST_VALID 0x8492A53C #define MAGIC_WORD_CANARY 0xDEADBEEF /*============================ MACROFIED FUNCTIONS ===========================*/ /*============================ TYPES =========================================*/ -/*! - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/*! - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - struct __task_cycle_info_t { task_cycle_info_t tInfo; //!< cycle information int64_t lLastTimeStamp; //!< previous timestamp @@ -165,66 +63,66 @@ struct __task_cycle_info_t { /*============================ GLOBAL VARIABLES ==============================*/ -extern uint32_t SystemCoreClock; - /*============================ LOCAL VARIABLES ===============================*/ volatile int64_t g_lLastTimeStamp = 0; volatile static int64_t s_lOldTimestamp; volatile int32_t g_nOffset = 0; -volatile static int32_t s_nUSUnit = 1; -volatile static int32_t s_nMSUnit = 1; -volatile static int32_t s_nMSResidule = 0; -volatile static int32_t s_nUSResidule = 0; -volatile static int32_t s_nSystemMS = 0; -volatile static int32_t s_nSystemUS = 0; +volatile static uint32_t s_wUSUnit = 1; +volatile static uint32_t s_wMSUnit = 1; +volatile static uint32_t s_wMSResidule = 0; +volatile static uint32_t s_wUSResidule = 0; +volatile static int64_t s_lSystemMS = 0; +volatile static int64_t s_lSystemUS = 0; volatile static int64_t s_lSystemClockCounts = 0; - /*============================ PROTOTYPES ====================================*/ -/*============================ IMPLEMENTATION ================================*/ -/*============================ INCLUDES ======================================*/ - -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - //__IRQ_SAFE { - SysTick->CTRL = 0; +/* low level interface for porting */ +extern +uint32_t perfc_port_get_system_timer_freq(void); +extern +int64_t perfc_port_get_system_timer_top(void); +extern +bool perfc_port_is_system_timer_ovf_pending(void); +extern +bool perfc_port_init_system_timer(bool bTimerOccupied); +extern +int64_t perfc_port_get_system_timer_elapsed(void); +extern +void perfc_port_clear_system_timer_ovf_pending(void); +extern +void perfc_port_stop_system_timer_counting(void); +extern +void perfc_port_clear_system_timer_counter(void); - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - //NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - //SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; - //} - return (0UL); /* Function successful */ -} +/*============================ IMPLEMENTATION ================================*/ +/*============================ INCLUDES ======================================*/ -void user_code_insert_to_systick_handler(void) +void perfc_port_insert_to_system_timer_insert_ovf_handler(void) { - uint32_t wLoad = SysTick->LOAD + 1; - s_lSystemClockCounts += wLoad; + int64_t lLoad = perfc_port_get_system_timer_top() + 1; + s_lSystemClockCounts += lLoad; // update system ms counter do { - s_nMSResidule += wLoad; - int32_t nMS = s_nMSResidule / s_nMSUnit; - s_nMSResidule -= nMS * s_nMSUnit; - s_nSystemMS += nMS; + int64_t lTemp = s_wMSResidule + lLoad; + + int64_t lMS = lTemp / s_wMSUnit; + s_lSystemMS += lMS; + s_wMSResidule = (uint32_t)((int64_t)lTemp - (int64_t)lMS * s_wMSUnit); + } while(0); // update system us counter do { - s_nUSResidule += wLoad; - int32_t nUS = s_nUSResidule / s_nUSUnit; - s_nUSResidule -= nUS * s_nUSUnit; - s_nSystemUS += nUS; + int64_t lTemp = s_wUSResidule + lLoad; + + int64_t lUS = lTemp / s_wUSUnit; + s_lSystemUS += lUS; + + s_wUSResidule = (uint32_t)((int64_t)lTemp - (int64_t)lUS * s_wUSUnit); + } while(0); } @@ -237,8 +135,9 @@ void __perf_os_patch_init(void) void update_perf_counter(void) { - s_nUSUnit = SystemCoreClock / 1000000ul; - s_nMSUnit = SystemCoreClock / 1000ul; + uint32_t wSystemFrequency = perfc_port_get_system_timer_freq(); + s_wUSUnit = wSystemFrequency / 1000000ul; + s_wMSUnit = wSystemFrequency / 1000ul; __IRQ_SAFE { g_lLastTimeStamp = get_system_ticks(); @@ -246,31 +145,32 @@ void update_perf_counter(void) } } - -void init_cycle_counter(bool bIsSysTickOccupied) +bool init_cycle_counter(bool bIsSysTickOccupied) { + bool bResult = false; __IRQ_SAFE { - if (!bIsSysTickOccupied) { - SysTick_Config(0x01000000); // use the longest period - } - SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + bResult = perfc_port_init_system_timer(bIsSysTickOccupied); // use the longest period + perfc_port_clear_system_timer_ovf_pending(); } update_perf_counter(); s_lSystemClockCounts = 0; // reset system cycle counter - s_nSystemMS = 0; // reset system millisecond counter - s_nSystemUS = 0; // reset system microsecond counter + s_lSystemMS = 0; // reset system millisecond counter + s_lSystemUS = 0; // reset system microsecond counter __perf_os_patch_init(); + + return bResult; } /*! \note this function should only be called when irq is disabled * hence SysTick-LOAD and (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) * won't change. */ -__STATIC_INLINE int32_t check_systick(void) +__STATIC_INLINE int64_t check_systick(void) { - int32_t nTemp = (int32_t)SysTick->LOAD - (int32_t)SysTick->VAL; + int64_t lLoad = perfc_port_get_system_timer_top() + 1; + int64_t lTemp = perfc_port_get_system_timer_elapsed(); /* Since we cannot stop counting temporarily, there are several * conditions which we should take into consideration: @@ -292,35 +192,32 @@ __STATIC_INLINE int32_t check_systick(void) * equals to) PERF_CNT_COMPENSATION_THRESHOLD. * The following code implements an equivalent logic. */ - if (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk){ - if (((int32_t)SysTick->LOAD - nTemp) >= PERF_CNT_COMPENSATION_THRESHOLD) { - nTemp += SysTick->LOAD + 1; + if (perfc_port_is_system_timer_ovf_pending()){ + if ((lLoad - lTemp) >= PERF_CNT_COMPENSATION_THRESHOLD) { + lTemp += lLoad; } } - return nTemp; + return lTemp; } void before_cycle_counter_reconfiguration(void) { __IRQ_SAFE { - SysTick->CTRL = 0; /* disable SysTick first */ + perfc_port_stop_system_timer_counting(); - if (SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) { /* pending SysTick exception */ - SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; /* clear pending bit */ + if (perfc_port_is_system_timer_ovf_pending()) { + perfc_port_clear_system_timer_ovf_pending(); /* clear pending bit */ user_code_insert_to_systick_handler(); /* manually handle exception */ } s_lSystemClockCounts = get_system_ticks(); /* get the final cycle counter value */ - SysTick->LOAD = 0UL; - SysTick->VAL = 0UL; /* clear the Current Value Register */ + perfc_port_clear_system_timer_counter(); } } - - __attribute__((constructor)) void __perf_counter_init(void) { @@ -328,9 +225,9 @@ void __perf_counter_init(void) } -void delay_us(int32_t nUs) +void delay_us(uint32_t wUs) { - int64_t lUs = (int64_t)nUs * (int64_t)s_nUSUnit; + int64_t lUs = (int64_t)wUs * (int64_t)s_wUSUnit; int32_t iCompensate = g_nOffset > PERF_CNT_DELAY_US_COMPENSATION ? g_nOffset : PERF_CNT_DELAY_US_COMPENSATION; @@ -345,22 +242,21 @@ void delay_us(int32_t nUs) while(get_system_ticks() < lUs); } - -void delay_ms(int32_t nMs) +void delay_ms(uint32_t wMs) { - int64_t lUs = (int64_t)nMs * (int64_t)s_nMSUnit; + int64_t lMs = (int64_t)wMs * (int64_t)s_wMSUnit; int32_t iCompensate = g_nOffset > PERF_CNT_DELAY_US_COMPENSATION ? g_nOffset : PERF_CNT_DELAY_US_COMPENSATION; - if (lUs <= iCompensate) { + if (lMs <= iCompensate) { return ; } - lUs -= iCompensate; + lMs -= iCompensate; - lUs += get_system_ticks(); - while(get_system_ticks() < lUs); + lMs += get_system_ticks(); + while(get_system_ticks() < lMs); } __attribute__((noinline)) @@ -420,47 +316,47 @@ int64_t clock(void) return get_system_ticks(); } -int32_t get_system_ms(void) +int64_t get_system_ms(void) { - int32_t nTemp = 0; + int64_t lTemp = 0; __IRQ_SAFE { - nTemp = s_nSystemMS + (check_systick() + s_nMSResidule) / s_nMSUnit; + lTemp = s_lSystemMS + ((check_systick() + (int64_t)s_wMSResidule) / s_wMSUnit); } - return nTemp; + return lTemp; } -int32_t get_system_us(void) +int64_t get_system_us(void) { - int32_t nTemp = 0; + int64_t lTemp = 0; __IRQ_SAFE { - nTemp = s_nSystemUS + (check_systick() + s_nUSResidule) / s_nUSUnit; + lTemp = s_lSystemUS + ((check_systick() + (int64_t)s_wUSResidule) / s_wUSUnit); } - return nTemp; + return lTemp; } int64_t perfc_convert_ticks_to_ms(int64_t lTick) { - return lTick / (int64_t)s_nMSUnit; + return lTick / (int64_t)s_wMSUnit; } int64_t perfc_convert_ms_to_ticks(uint32_t wMS) { - int64_t lResult = (int64_t)s_nMSUnit * (int64_t)wMS; + int64_t lResult = (int64_t)s_wMSUnit * (int64_t)wMS; return lResult ? lResult : 1; } int64_t perfc_convert_ticks_to_us(int64_t lTick) { - return lTick / (int64_t)s_nUSUnit; + return lTick / (int64_t)s_wUSUnit; } int64_t perfc_convert_us_to_ticks(uint32_t wMS) { - int64_t lResult = (int64_t)s_nUSUnit * (int64_t)wMS; + int64_t lResult = (int64_t)s_wUSUnit * (int64_t)wMS; return lResult ? lResult : 1; } @@ -504,7 +400,7 @@ uint32_t EventRecorderTimerSetup (void) /// \return timer frequency in Hz uint32_t EventRecorderTimerGetFreq (void) { - return SystemCoreClock; + return perfc_port_get_system_timer_freq(); } /// Get timer count. diff --git a/perf_counter.h b/perf_counter.h index 5d8eb0a..43ee5b1 100644 --- a/perf_counter.h +++ b/perf_counter.h @@ -1,5 +1,5 @@ /**************************************************************************** -* Copyright 2022 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * * * * Licensed under the Apache License, Version 2.0 (the "License"); * * you may not use this file except in compliance with the License. * @@ -22,7 +22,12 @@ #include #include #include -#include "cmsis_compiler.h" + +#ifndef __PERFC_CFG_PORTING_INCLUDE__ +# include "perfc_port_default.h" +#else +# include __PERFC_CFG_PORTING_INCLUDE__ +#endif #ifdef __cplusplus extern "C" { @@ -34,8 +39,8 @@ extern "C" { * @{ */ #define __PERF_COUNTER_VER_MAJOR__ 2 -#define __PERF_COUNTER_VER_MINOR__ 2 -#define __PERF_COUNTER_VER_REVISE__ 4 +#define __PERF_COUNTER_VER_MINOR__ 3 +#define __PERF_COUNTER_VER_REVISE__ 0 #define __PERF_COUNTER_VER_STR__ "" @@ -134,6 +139,33 @@ extern "C" { # define UNUSED_PARAM(__VAR) (void)(__VAR) #endif +#ifndef MIN +# define MIN(__a, __b) ((__a) <= (__b) ? (__a) : (__b)) +#endif + +#ifndef MAX +# define MAX(__a, __b) ((__a) >= (__b) ? (__a) : (__b)) +#endif + +/*! + * \brief an attribute for static variables that no initialisation is required + * in the C startup process. + */ +#ifndef PERF_NOINIT +# if defined(__IS_COMPILER_ARM_COMPILER_5__) +# define PERF_NOINIT __attribute__(( section( ".bss.noinit"),zero_init)) +# elif defined(__IS_COMPILER_ARM_COMPILER_6__) +# define PERF_NOINIT __attribute__(( section( ".bss.noinit"))) +# elif defined(__IS_COMPILER_IAR__) +# define PERF_NOINIT __no_init +# elif (defined(__IS_COMPILER_GCC__) || defined(__IS_COMPILER_LLVM__)) && !defined(__APPLE__) +# define PERF_NOINIT __attribute__(( section( ".bss.noinit"))) +# else +# define PERF_NOINIT +# endif +#endif + + #undef __CONNECT2 #undef __CONNECT3 #undef __CONNECT4 @@ -265,26 +297,26 @@ extern "C" { #ifndef safe_atom_code # define safe_atom_code() \ - using( uint32_t SAFE_NAME(temp) = \ - ({ uint32_t SAFE_NAME(temp2)=__get_PRIMASK(); \ - __disable_irq(); \ - SAFE_NAME(temp2);}), \ - __set_PRIMASK(SAFE_NAME(temp))) + using( perfc_global_interrupt_status_t SAFE_NAME(temp) = \ + perfc_port_disable_global_interrupt(), \ + perfc_port_resume_global_interrupt(SAFE_NAME(temp))) #endif #ifndef __IRQ_SAFE # define __IRQ_SAFE \ - using( uint32_t SAFE_NAME(temp) = \ - ({ uint32_t SAFE_NAME(temp2)=__get_PRIMASK(); \ - __disable_irq(); \ - SAFE_NAME(temp2);}), \ - __set_PRIMASK(SAFE_NAME(temp))) + using( perfc_global_interrupt_status_t SAFE_NAME(temp) = \ + perfc_port_disable_global_interrupt(), \ + perfc_port_resume_global_interrupt(SAFE_NAME(temp))) #endif #ifndef __perf_counter_printf__ # define __perf_counter_printf__ printf #endif +/* deprecated macro for backward compatibility */ +#define user_code_insert_to_systick_handler \ + perfc_port_insert_to_system_timer_insert_ovf_handler + #if __PLOOC_VA_NUM_ARGS() != 0 #warning Please enable GNU extensions, it is required by __cycleof__() and \ __super_loop_monitor__() @@ -331,7 +363,7 @@ __asm(".global __ensure_systick_wrapper\n\t"); __perf_counter_printf__( \ "--------------------------------------------\r\n"); \ __perf_counter_printf__( \ - __STR " total cycle count: %ld [%016lx]\r\n", \ + __STR " total cycle count: %ld [%08lx]\r\n", \ (long)_, (long)_); \ } else { \ __VA_ARGS__ \ @@ -348,18 +380,18 @@ __asm(".global __ensure_systick_wrapper\n\t"); E.g. \code while (1) { - __cpu_time__(100) { + __cpu_usage__(100) { delay_us(5000); } delay_us(5000); } \endcode */ -#define __cpu_time__(__CNT, ...) \ +#define __cpu_usage__(__CNT, ...) \ static int64_t SAFE_NAME(s_lTimestamp) = 0, SAFE_NAME(s_lTotal) = 0; \ - static uint32_t s_wLoopCounter = (__CNT); \ + static uint32_t SAFE_NAME(s_wLoopCounter) = (__CNT); \ using(float __usage__ = 0, ({ \ - if (0 == s_wLoopCounter) { \ + if (0 == SAFE_NAME(s_wLoopCounter)) { \ __usage__ = (float)((double)SAFE_NAME(s_lTotal) \ / (double)( get_system_ticks() \ - SAFE_NAME(s_lTimestamp))); \ @@ -367,18 +399,20 @@ __asm(".global __ensure_systick_wrapper\n\t"); SAFE_NAME(s_lTimestamp) = 0; \ SAFE_NAME(s_lTotal) = 0; \ if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ - __perf_counter_printf__("CPU Usage %3.2f%%\r\n", (double)__usage__); \ + __perf_counter_printf__("CPU Usage %3.2f%%\r\n", (double)__usage__);\ } else { \ __VA_ARGS__ \ } \ } \ if (0 == SAFE_NAME(s_lTimestamp)) { \ SAFE_NAME(s_lTimestamp) = get_system_ticks(); \ - s_wLoopCounter = (__CNT); \ + SAFE_NAME(s_wLoopCounter) = (__CNT); \ } \ start_task_cycle_counter();}), \ ({SAFE_NAME(s_lTotal) += stop_task_cycle_counter(); \ - s_wLoopCounter--;})) + SAFE_NAME(s_wLoopCounter)--;})) + +#define __cpu_time__ __cpu_usage__ /*! * \addtogroup gBasicTimerService 1.2 Timer Service @@ -555,7 +589,6 @@ extern volatile int32_t g_nOffset; /*============================ PROTOTYPES ====================================*/ - /*! * \addtogroup gBasicTicks 1.1 Ticks APIs * \ingroup gBasic @@ -601,7 +634,7 @@ extern int64_t clock(void); /*! * \brief try to set a start pointer for the performance counter */ -__STATIC_INLINE +static inline void start_cycle_counter(void) { g_lLastTimeStamp = get_system_ticks(); @@ -612,7 +645,7 @@ void start_cycle_counter(void) * \note you can have multiple stop_cycle_counter following one start point * \return int32_t the elapsed cycle count */ -__STATIC_INLINE +static inline int64_t stop_cycle_counter(void) { int64_t lTemp = (get_system_ticks() - g_lLastTimeStamp); @@ -634,29 +667,27 @@ int64_t stop_cycle_counter(void) /*! * \brief get the elapsed milliseconds since perf_counter is initialised - * \return int32_t the elapsed milliseconds + * \return int64_t the elapsed milliseconds */ -extern int32_t get_system_ms(void); +extern int64_t get_system_ms(void); /*! * \brief get the elapsed microsecond since perf_counter is initialised - * \return int32_t the elapsed microsecond + * \return int64_t the elapsed microsecond */ -extern int32_t get_system_us(void); - - +extern int64_t get_system_us(void); /*! * \brief delay specified time in microsecond - * \param[in] nUs time in microsecond + * \param[in] wUs time in microsecond */ -extern void delay_us(int32_t nUs); +extern void delay_us(uint32_t wUs); /*! * \brief delay specified time in millisecond - * \param[in] nMs time in millisecond + * \param[in] wMs time in millisecond */ -extern void delay_ms(int32_t nMs); +extern void delay_ms(uint32_t nMs); /*! * \brief convert ticks of a reference timer to millisecond @@ -875,12 +906,16 @@ extern int64_t __stop_task_cycle_counter(task_cycle_info_t *ptInfo); * * \param[in] bIsSysTickOccupied A boolean value which indicates whether SysTick * is already used by user application. + * + * \return false Failed to initialize the timer counter, as the timer is not + * available or IO error. + * \return true initialization is successful. */ -extern void init_cycle_counter(bool bIsSysTickOccupied); +extern bool init_cycle_counter(bool bIsSysTickOccupied); /*! - * \brief a system timer handler inserted to the SysTick_Handler + * \brief a system timer overflow handler * * \note - if you are using a compiler other than armcc or armclang, e.g. iar, * arm gcc etc, the systick_wrapper_ual.o doesn't work with the linker @@ -893,7 +928,7 @@ extern void init_cycle_counter(bool bIsSysTickOccupied); * you do NOT have to insert this function into your SysTick_Handler, * the systick_wrapper_ual.s will do the work for you. */ -extern void user_code_insert_to_systick_handler(void); +extern void perfc_port_insert_to_system_timer_insert_ovf_handler(void); /*! * \brief update perf_counter as SystemCoreClock has been updated. @@ -943,5 +978,4 @@ void coremark_main(void); #ifdef __cplusplus } #endif - #endif diff --git a/perfc_port_default.c b/perfc_port_default.c new file mode 100644 index 0000000..1b05652 --- /dev/null +++ b/perfc_port_default.c @@ -0,0 +1,230 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ +#undef __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__ + +#include +#include +#include +#include "cmsis_compiler.h" + +#define __IMPLEMENT_PERF_COUNTER +#include "perf_counter.h" + +#if defined(__IS_COMPILER_GCC__) +# pragma GCC diagnostic ignored "-Wattributes" +#endif + +#if defined(__clang__) +# pragma clang diagnostic ignored "-Wunknown-warning-option" +# pragma clang diagnostic ignored "-Wreserved-identifier" +# pragma clang diagnostic ignored "-Wconditional-uninitialized" +# pragma clang diagnostic ignored "-Wcast-align" +# pragma clang diagnostic ignored "-Wmissing-prototypes" +#endif + + +/*============================ MACROS ========================================*/ + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#ifndef __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ +# define __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ 0 +#endif + +/*============================ MACROFIED FUNCTIONS ===========================*/ +/*============================ TYPES =========================================*/ + +/*! + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/*! + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + + + +/*============================ GLOBAL VARIABLES ==============================*/ +extern uint32_t SystemCoreClock; + +/*============================ LOCAL VARIABLES ===============================*/ +/*============================ PROTOTYPES ====================================*/ +/*============================ IMPLEMENTATION ================================*/ +/*============================ INCLUDES ======================================*/ + +#if !__PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ +__WEAK +bool perfc_port_init_system_timer(bool bTimerOccupied) +{ + do { + if (bTimerOccupied) { + break; + } + + __IRQ_SAFE { + SysTick->CTRL = 0; + + SysTick->LOAD = SysTick_LOAD_RELOAD_Msk; /* set reload register */ + //NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + //SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; + } + } while(0); + + return true; +} + +__WEAK +uint32_t perfc_port_get_system_timer_freq(void) +{ + return SystemCoreClock; +} + +__WEAK +bool perfc_port_is_system_timer_ovf_pending(void) +{ + return SCB->ICSR & SCB_ICSR_PENDSTSET_Msk; +} + +__WEAK +int64_t perfc_port_get_system_timer_top(void) +{ + return SysTick->LOAD; +} + +__WEAK +int64_t perfc_port_get_system_timer_elapsed(void) +{ + return (int64_t)SysTick->LOAD - (uint32_t)SysTick->VAL; +} + +__WEAK +void perfc_port_clear_system_timer_ovf_pending(void) +{ + SCB->ICSR = SCB_ICSR_PENDSTCLR_Msk; +} + +__WEAK +void perfc_port_stop_system_timer_counting(void) +{ + SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; +} + +__WEAK +void perfc_port_clear_system_timer_counter(void) +{ + SysTick->VAL = 0UL; +} + +#endif + + diff --git a/perfc_port_default.h b/perfc_port_default.h new file mode 100644 index 0000000..e7fedac --- /dev/null +++ b/perfc_port_default.h @@ -0,0 +1,53 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ + +#ifndef __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ +# define __PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ 0 +#endif + +#if !__PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ + +#include "cmsis_compiler.h" + +/*============================ MACROS ========================================*/ +/*============================ MACROFIED FUNCTIONS ===========================*/ +/*============================ TYPES =========================================*/ +typedef uint32_t perfc_global_interrupt_status_t; + +/*============================ GLOBAL VARIABLES ==============================*/ +/*============================ LOCAL VARIABLES ===============================*/ +/*============================ PROTOTYPES ====================================*/ +/*============================ IMPLEMENTATION ================================*/ + +__STATIC_INLINE +perfc_global_interrupt_status_t perfc_port_disable_global_interrupt(void) +{ + perfc_global_interrupt_status_t tStatus = __get_PRIMASK(); + __disable_irq(); + + return tStatus; +} + +__STATIC_INLINE +void perfc_port_resume_global_interrupt(perfc_global_interrupt_status_t tStatus) +{ + __set_PRIMASK(tStatus); +} + +#endif diff --git a/perfc_port_pmu.c b/perfc_port_pmu.c new file mode 100644 index 0000000..685e1db --- /dev/null +++ b/perfc_port_pmu.c @@ -0,0 +1,1769 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ +#undef __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__ + +#include +#include +#include + +#define __IMPLEMENT_PERF_COUNTER +#include "perf_counter.h" + +#if defined(__IS_COMPILER_GCC__) +# pragma GCC diagnostic ignored "-Wattributes" +#endif + +#if defined(__clang__) +# pragma clang diagnostic ignored "-Wunknown-warning-option" +# pragma clang diagnostic ignored "-Wreserved-identifier" +# pragma clang diagnostic ignored "-Wconditional-uninitialized" +# pragma clang diagnostic ignored "-Wcast-align" +# pragma clang diagnostic ignored "-Wmissing-prototypes" +#endif + +#if defined(_RTE_) +# include "RTE_Components.h" +#endif + + +/*============================ MACROS ========================================*/ + +#if defined(CMSIS_device_header) +# include CMSIS_device_header +#else + +#ifndef __PMU_NUM_EVENTCNT +# define __PMU_NUM_EVENTCNT 8 +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/** \brief DCB Debug Halting Control and Status Register Definitions */ +#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ +#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ + +#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ +#define DCB_DHCSR_S_RESTART_ST_Msk (1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ + +#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ +#define DCB_DHCSR_S_RESET_ST_Msk (1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ + +#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ +#define DCB_DHCSR_S_RETIRE_ST_Msk (1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ + +#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ +#define DCB_DHCSR_S_FPD_Msk (1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ + +#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_SUIDE_Msk (1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ +#define DCB_DHCSR_S_NSUIDE_Msk (1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ + +#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ +#define DCB_DHCSR_S_SDE_Msk (1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ + +#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ +#define DCB_DHCSR_S_LOCKUP_Msk (1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ + +#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ +#define DCB_DHCSR_S_SLEEP_Msk (1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ + +#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ +#define DCB_DHCSR_S_HALT_Msk (1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ + +#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ +#define DCB_DHCSR_S_REGRDY_Msk (1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ + +#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ +#define DCB_DHCSR_C_PMOV_Msk (1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ + +#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ +#define DCB_DHCSR_C_SNAPSTALL_Msk (1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ + +#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ +#define DCB_DHCSR_C_MASKINTS_Msk (1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ + +#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ +#define DCB_DHCSR_C_STEP_Msk (1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ + +#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ +#define DCB_DHCSR_C_HALT_Msk (1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ + +#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ +#define DCB_DHCSR_C_DEBUGEN_Msk (1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ + +/** \brief DCB Debug Core Register Selector Register Definitions */ +#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ +#define DCB_DCRSR_REGWnR_Msk (1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ + +#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ +#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ + +/** \brief DCB Debug Core Register Data Register Definitions */ +#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ +#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ + +/** \brief DCB Debug Exception and Monitor Control Register Definitions */ +#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ +#define DCB_DEMCR_TRCENA_Msk (1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ + +#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ +#define DCB_DEMCR_MONPRKEY_Msk (1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ + +#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ +#define DCB_DEMCR_UMON_EN_Msk (1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ + +#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ +#define DCB_DEMCR_SDME_Msk (1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ + +#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ +#define DCB_DEMCR_MON_REQ_Msk (1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ + +#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ +#define DCB_DEMCR_MON_STEP_Msk (1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ + +#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ +#define DCB_DEMCR_MON_PEND_Msk (1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ + +#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ +#define DCB_DEMCR_MON_EN_Msk (1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ + +#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ +#define DCB_DEMCR_VC_SFERR_Msk (1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ + +#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ +#define DCB_DEMCR_VC_HARDERR_Msk (1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ + +#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ +#define DCB_DEMCR_VC_INTERR_Msk (1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ + +#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ +#define DCB_DEMCR_VC_BUSERR_Msk (1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ + +#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ +#define DCB_DEMCR_VC_STATERR_Msk (1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ + +#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ +#define DCB_DEMCR_VC_CHKERR_Msk (1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ + +#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ +#define DCB_DEMCR_VC_NOCPERR_Msk (1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ + +#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ +#define DCB_DEMCR_VC_MMERR_Msk (1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ + +#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ +#define DCB_DEMCR_VC_CORERESET_Msk (1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ + +/** \brief DCB Debug Set Clear Exception and Monitor Control Register Definitions */ +#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ +#define DCB_DSCEMCR_CLR_MON_REQ_Msk (1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ + +#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ +#define DCB_DSCEMCR_CLR_MON_PEND_Msk (1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ + +#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ +#define DCB_DSCEMCR_SET_MON_REQ_Msk (1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ + +#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ +#define DCB_DSCEMCR_SET_MON_PEND_Msk (1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ + +/** \brief DCB Debug Authentication Control Register Definitions */ +#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ +#define DCB_DAUTHCTRL_UIDEN_Msk (1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ + +#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ +#define DCB_DAUTHCTRL_UIDAPEN_Msk (1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ + +#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ +#define DCB_DAUTHCTRL_FSDMA_Msk (1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ + +#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ + +#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ +#define DCB_DAUTHCTRL_INTSPIDEN_Msk (1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ + +#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ +#define DCB_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ + +/** \brief DCB Debug Security Control and Status Register Definitions */ +#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ +#define DCB_DSCSR_CDSKEY_Msk (1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ + +#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ +#define DCB_DSCSR_CDS_Msk (1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ + +#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ +#define DCB_DSCSR_SBRSEL_Msk (1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ + +#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ +#define DCB_DSCSR_SBRSELEN_Msk (1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** \brief SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ +#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ + +#endif + + +#if !defined(__PMU_PRESENT) || (0 == __PMU_PRESENT) +/** \brief PMU Event Counter Registers (0-30) Definitions */ +#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ +#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ + +/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ +#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ +#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ + +/** \brief PMU Count Enable Set Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ +#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ + +#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ +#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ + +#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ +#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ + +#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ +#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ + +#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ +#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ + +#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ +#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ + +#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ +#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ + +#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ +#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ + +#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ +#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ + +#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ +#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ + +#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ +#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ + +#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ +#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ + +#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ +#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ + +#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ +#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ + +#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ +#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ + +#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ +#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ + +#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ +#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ + +#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ +#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ + +#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ +#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ + +#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ +#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ + +#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ +#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ + +#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ +#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ + +#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ +#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ + +#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ +#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ + +#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ +#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ + +#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ +#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ + +#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ +#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ + +#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ +#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ + +#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ +#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ + +#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ +#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ + +#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ +#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ + +#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ +#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ + +/** \brief PMU Count Enable Clear Register Definitions */ +#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ +#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ +#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ + +#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ +#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ +#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ +#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ +#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ +#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ +#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ +#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ +#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ +#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ +#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ +#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ +#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ +#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ +#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ +#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ +#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ +#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ +#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ +#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ +#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ +#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ +#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ +#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ +#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ +#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ +#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ +#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ +#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ + +#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ +#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ + +#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ +#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ + +/** \brief PMU Interrupt Enable Set Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ +#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ + +#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ +#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ + +/** \brief PMU Interrupt Enable Clear Register Definitions */ +#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ + +#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ + +#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ +#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ + +/** \brief PMU Overflow Flag Status Set Register Definitions */ +#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ +#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ + +#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ +#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ + +#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ +#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ + +#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ +#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ + +#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ +#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ + +#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ +#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ + +#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ +#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ + +#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ +#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ + +#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ +#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ + +#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ +#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ + +#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ +#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ + +#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ +#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ + +#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ +#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ + +#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ +#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ + +#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ +#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ + +#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ +#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ + +#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ +#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ + +#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ +#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ + +#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ +#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ + +#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ +#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ + +#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ +#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ + +#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ +#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ + +#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ +#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ + +#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ +#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ + +#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ +#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ + +#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ +#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ + +#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ +#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ + +#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ +#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ + +#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ +#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ + +#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ +#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ + +#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ +#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ + +#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ +#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ + +/** \brief PMU Overflow Flag Status Clear Register Definitions */ +#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ +#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ +#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ + +#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ +#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ +#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ +#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ +#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ +#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ +#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ +#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ +#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ +#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ +#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ +#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ +#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ +#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ +#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ +#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ +#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ +#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ +#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ +#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ +#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ +#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ +#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ +#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ +#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ +#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ +#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ +#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ +#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ + +#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ +#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ + +#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ +#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ + +/** \brief PMU Software Increment Counter */ +#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ +#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ + +#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ +#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ + +#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ +#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ + +#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ +#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ + +#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ +#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ + +#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ +#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ + +#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ +#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ + +#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ +#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ + +#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ +#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ + +#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ +#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ + +#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ +#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ + +#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ +#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ + +#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ +#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ + +#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ +#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ + +#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ +#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ + +#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ +#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ + +#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ +#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ + +#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ +#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ + +#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ +#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ + +#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ +#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ + +#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ +#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ + +#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ +#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ + +#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ +#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ + +#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ +#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ + +#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ +#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ + +#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ +#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ + +#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ +#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ + +#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ +#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ + +#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ +#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ + +#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ +#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ + +#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ +#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ + +/** \brief PMU Control Register Definitions */ +#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ +#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ + +#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ +#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ +#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ + +#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ +#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ + +#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ +#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ + +#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ +#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ + +/** \brief PMU Type Register Definitions */ +#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ +#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ + +#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ +#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ + +#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ +#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ + +#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ +#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ + +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ +#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ + +/** \brief PMU Authentication Status Register Definitions */ +#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ +#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ +#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ + +#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ +#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ + +/** + * \brief PMU Events + * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. + * */ + +#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ +#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ +#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ +#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ +#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ +#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ +#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ +#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ +#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ +#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ +#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ +#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ +#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ +#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ +#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ +#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ +#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ +#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ +#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ +#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ +#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ +#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ +#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ +#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ +#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ +#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ +#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ +#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ +#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ +#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ +#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ +#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ +#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ +#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ +#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ +#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ +#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ +#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ +#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ +#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ +#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ +#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ +#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ +#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ +#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ +#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ +#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ +#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ +#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ +#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ +#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ +#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ +#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ +#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ +#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ +#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ +#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ +#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ +#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ +#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ +#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ +#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ +#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ +#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ +#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ +#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ +#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ +#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ +#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ +#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ +#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ +#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ +#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ +#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ +#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ +#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ +#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ +#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ +#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ +#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ +#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ +#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ +#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ +#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ +#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ +#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ +#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ + +#endif + + +#ifndef PMU +# define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ +# define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ +#endif + +#ifndef DCB +# define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ +# define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ +#endif + +#ifndef SCB +# define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +# define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ +# define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#endif + +#ifndef DWT +# define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +# define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#endif + + +/*============================ MACROFIED FUNCTIONS ===========================*/ +/*============================ TYPES =========================================*/ + +#if !defined(CMSIS_device_header) +/** + \brief Structure type to access the Debug Control Block Registers (DCB). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} DCB_Type; + +/*! + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; +#endif + +#if !defined(__PMU_PRESENT) || (0 == __PMU_PRESENT) +/** + \brief Structure type to access the Performance Monitoring Unit (PMU). + */ +typedef struct +{ + __IOM uint32_t EVCNTR[31]; /*!< Offset: 0x0 (R/W) Event Counter Registers */ + __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) Cycle Counter Register */ + uint32_t RESERVED1[224]; + __IOM uint32_t EVTYPER[31]; /*!< Offset: 0x400 (R/W) Event Type and Filter Registers */ + __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) Cycle Counter Filter Register */ + uint32_t RESERVED3[480]; + __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) Count Enable Set Register */ + uint32_t RESERVED4[7]; + __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) Count Enable Clear Register */ + uint32_t RESERVED5[7]; + __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) Interrupt Enable Set Register */ + uint32_t RESERVED6[7]; + __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) Interrupt Enable Clear Register */ + uint32_t RESERVED7[7]; + __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) Overflow Flag Status Clear Register */ + uint32_t RESERVED8[7]; + __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) Software Increment Register */ + uint32_t RESERVED9[7]; + __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) Overflow Flag Status Set Register */ + uint32_t RESERVED10[79]; + __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) Control Register */ + uint32_t RESERVED11[108]; + __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) Authentication Status Register */ + __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) Device Architecture Register */ + uint32_t RESERVED12[3]; + __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) Device Type Register */ +} PMU_Type; +#endif + +enum { + PMU_CNT_INSTRUCTION = 0, + PMU_CNT_MEM_ACCESS = 1, + PMU_CNT_L1_DCACHE_REFILL = 2, +}; + +/*============================ GLOBAL VARIABLES ==============================*/ +/*============================ LOCAL VARIABLES ===============================*/ + +#if __PMU_NUM_EVENTCNT >= 6 +# define __COUNTER_NUM__ (3 + (__PMU_NUM_EVENTCNT - 6)) +#elif __PMU_NUM_EVENTCNT > 2 +# define __COUNTER_NUM__ (__PMU_NUM_EVENTCNT >> 1) +#else +# define __COUNTER_NUM__ (5) +#endif + + +static volatile uint64_t s_dwEventCounter[__COUNTER_NUM__] = {0}; + +/*============================ PROTOTYPES ====================================*/ +/* low level interface for porting */ +extern +uint32_t perfc_port_get_system_timer_freq(void); +extern +int64_t perfc_port_get_system_timer_top(void); +extern +bool perfc_port_is_system_timer_ovf_pending(void); +extern +bool perfc_port_init_system_timer(bool bTimerOccupied); +extern +int64_t perfc_port_get_system_timer_elapsed(void); +extern +void perfc_port_clear_system_timer_ovf_pending(void); +extern +void perfc_port_stop_system_timer_counting(void); +extern +void perfc_port_clear_system_timer_counter(void); + +/*============================ INCLUDES ======================================*/ +/*============================ IMPLEMENTATION ================================*/ + + +#if __PERFC_USE_PMU_PORTING__ + +__USED +void DebugMon_Handler(void) +{ + perfc_port_pmu_insert_to_debug_monitor_handler(); +} + +void perfc_port_pmu_insert_to_debug_monitor_handler(void) +{ + if (!(SCB->DFSR & SCB_DFSR_PMU_Msk)) { + return ; + } + + if (perfc_port_is_system_timer_ovf_pending()) { + perfc_port_clear_system_timer_ovf_pending(); + + perfc_port_insert_to_system_timer_insert_ovf_handler(); + } + + /* get number of counters */ + uint_fast8_t chCounter = PMU->TYPE & PMU_TYPE_NUM_CNTS_Msk; + chCounter = MIN(chCounter, __PMU_NUM_EVENTCNT); + + do { + /* handle counter 1 */ + if (chCounter < 2) { + break ; + } + if (PMU->OVSCLR & PMU_OVSCLR_CNT1_STATUS_Msk) { + PMU->OVSCLR = PMU_OVSCLR_CNT1_STATUS_Msk; + + s_dwEventCounter[PMU_CNT_INSTRUCTION] += (uint64_t)0x100000000; + } + + + /* handle counter 3 */ + if (chCounter < 4) { + break ; + } + if (PMU->OVSCLR & PMU_OVSCLR_CNT3_STATUS_Msk) { + PMU->OVSCLR = PMU_OVSCLR_CNT3_STATUS_Msk; + + s_dwEventCounter[PMU_CNT_MEM_ACCESS] += (uint64_t)0x100000000; + } + + + /* handle counter 5 */ + if (chCounter < 6) { + break ; + } + if (PMU->OVSCLR & PMU_OVSCLR_CNT5_STATUS_Msk) { + PMU->OVSCLR = PMU_OVSCLR_CNT5_STATUS_Msk; + + s_dwEventCounter[PMU_CNT_L1_DCACHE_REFILL] += (uint64_t)0x100000000; + } + + if (chCounter > 6) { + + for (uint_fast8_t n = 6; n < chCounter; n++) { + uint32_t wMask = (1<OVSSET & wMask) { + /* counter overflow is detected */ + PMU->OVSCLR = wMask; /* clear Overflow Flag */ + + /* update corresponding counter */ + s_dwEventCounter[n - 3] += 0x10000; + } + } + } + } while(0); +} + +bool perfc_port_init_system_timer(bool bIsTimeOccupied) +{ + UNUSED_PARAM(bIsTimeOccupied); + + if (!(PMU->TYPE & PMU_TYPE_CYCCNT_PRESENT_Msk)) { + return false; + } + + __IRQ_SAFE { + + PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; + + perfc_port_stop_system_timer_counting(); + + /* disable PMU Cycle Counter interrupt */ + PMU->INTENCLR = PMU_INTENCLR_CYCCNT_ENABLE_Msk; + + perfc_port_clear_system_timer_counter(); + perfc_port_clear_system_timer_ovf_pending(); + + /* reset all event counter */ + PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; + + /* configure event counter */ + do { + uint_fast8_t chCounter = PMU->TYPE & PMU_TYPE_NUM_CNTS_Msk; + chCounter = MIN(chCounter, __PMU_NUM_EVENTCNT); + + if (chCounter >= 2) { + /* 32 bit counter for instruction architecturally executed */ + PMU->EVTYPER[0] = ARM_PMU_INST_RETIRED; + PMU->EVTYPER[1] = ARM_PMU_CHAIN; + + /* clear counter 0/1 overflow flag */ + PMU->OVSCLR = PMU_OVSCLR_CNT0_STATUS_Msk + | PMU_OVSCLR_CNT1_STATUS_Msk; + + /* enable counter 1 interrupt */ + PMU->INTENSET = PMU_INTENSET_CNT1_ENABLE_Msk; + + /* enable counter 0/1 */ + PMU->CNTENSET = PMU_CNTENSET_CNT0_ENABLE_Msk + | PMU_CNTENSET_CNT1_ENABLE_Msk; + } + + if (chCounter >= 4) { + /* 32bit counter for all Data memory Accesses */ + PMU->EVTYPER[2] = ARM_PMU_MEM_ACCESS; + PMU->EVTYPER[3] = ARM_PMU_CHAIN; + + /* clear counter 2/3 overflow flag */ + PMU->OVSCLR = PMU_OVSCLR_CNT2_STATUS_Msk + | PMU_OVSCLR_CNT3_STATUS_Msk; + + /* enable counter 3 interrupt */ + PMU->INTENSET = PMU_INTENSET_CNT3_ENABLE_Msk; + + /* enable counter 2/3 */ + PMU->CNTENSET = PMU_CNTENSET_CNT2_ENABLE_Msk + | PMU_CNTENSET_CNT3_ENABLE_Msk; + } + + if (chCounter >= 6) { + /* 32bit counter for all Data memory Accesses */ + PMU->EVTYPER[4] = ARM_PMU_L1D_CACHE_REFILL; + PMU->EVTYPER[5] = ARM_PMU_CHAIN; + + /* clear counter 4/5 overflow flag */ + PMU->OVSCLR = PMU_OVSCLR_CNT4_STATUS_Msk + | PMU_OVSCLR_CNT5_STATUS_Msk; + + /* enable counter 5 interrupt */ + PMU->INTENSET = PMU_INTENSET_CNT5_ENABLE_Msk; + + /* enable counter 4/5 */ + PMU->CNTENSET = PMU_CNTENSET_CNT4_ENABLE_Msk + | PMU_CNTENSET_CNT5_ENABLE_Msk; + + } + + if (chCounter > 6) { + for (uint_fast8_t n = 6; n < chCounter; n++) { + uint32_t wMask = (1<OVSCLR = wMask; /* clear overflow flag */ + PMU->INTENSET = wMask; /* enable interrupt */ + PMU->CNTENSET = wMask; /* enable counter */ + } + } + + } while(0); + + DCB->DEMCR |= DCB_DEMCR_UMON_EN_Msk | + DCB_DEMCR_SDME_Msk | + DCB_DEMCR_TRCENA_Msk | + DCB_DEMCR_MON_EN_Msk ; + + /* enable PMU Cycle Counter interrupt */ + PMU->INTENSET = PMU_INTENSET_CCYCNT_ENABLE_Msk; + + PMU->CNTENSET = PMU_CNTENSET_CCNTR_ENABLE_Msk; + PMU->CTRL |= PMU_CTRL_ENABLE_Msk; + + /* force to disable DWT */ + DWT->CTRL = 0; + } + + return true; +} + +uint64_t perfc_pmu_get_instruction_count(void) +{ + uint32_t wHigh16, wLow16; + uint64_t dwResult; + bool bIsOverflow = false; + __IRQ_SAFE { + do { + wHigh16 = PMU->EVCNTR[1]; + wLow16 = PMU->EVCNTR[0]; + } while(wHigh16 < PMU->EVCNTR[1]); + dwResult = s_dwEventCounter[PMU_CNT_INSTRUCTION]; + bIsOverflow = (0 != (PMU->OVSCLR & PMU_OVSCLR_CNT1_STATUS_Msk)); + } + + dwResult += wLow16 | (wHigh16 << 16); + + if (bIsOverflow) { + dwResult += (uint64_t)1<<32; + } + + /* force to disable DWT */ + DWT->CTRL = 0; + + return dwResult; +} + +uint64_t perfc_pmu_get_memory_access_count(void) +{ + uint32_t wHigh16, wLow16; + uint64_t dwResult; + bool bIsOverflow = false; + + __IRQ_SAFE { + do { + wHigh16 = PMU->EVCNTR[3]; + wLow16 = PMU->EVCNTR[2]; + } while(wHigh16 < PMU->EVCNTR[3]); + dwResult = s_dwEventCounter[PMU_CNT_MEM_ACCESS]; + bIsOverflow = (0 != (PMU->OVSCLR & PMU_OVSCLR_CNT3_STATUS_Msk)); + } + + dwResult += wLow16 | (wHigh16 << 16); + + if (bIsOverflow) { + dwResult += (uint64_t)1<<32; + } + + /* force to disable DWT */ + DWT->CTRL = 0; + + return dwResult; +} + + +uint64_t perfc_pmu_get_L1_dcache_refill_count(void) +{ + uint32_t wHigh16, wLow16; + uint64_t dwResult; + bool bIsOverflow = false; + + __IRQ_SAFE { + do { + wHigh16 = PMU->EVCNTR[5]; + wLow16 = PMU->EVCNTR[4]; + } while(wHigh16 < PMU->EVCNTR[5]); + dwResult = s_dwEventCounter[PMU_CNT_L1_DCACHE_REFILL]; + bIsOverflow = (0 != (PMU->OVSCLR & PMU_OVSCLR_CNT5_STATUS_Msk)); + } + + dwResult += wLow16 | (wHigh16 << 16); + + if (bIsOverflow) { + dwResult += (uint64_t)1<<32; + } + + /* force to disable DWT */ + DWT->CTRL = 0; + + return dwResult; +} + +uint32_t perfc_port_get_system_timer_freq(void) +{ + extern uint32_t SystemCoreClock; + + /* return the system timer frequency */ + return SystemCoreClock; +} + +bool perfc_port_is_system_timer_ovf_pending(void) +{ + /* whether the system timer overflow is pending */ + return PMU->OVSSET & PMU_OVSSET_CYCCNT_STATUS_Msk; +} + +int64_t perfc_port_get_system_timer_top(void) +{ + /* the top value of the counting */ + return 0xFFFFFFFF; +} + +int64_t perfc_port_get_system_timer_elapsed(void) +{ + return (int64_t)PMU->CCNTR;//ARM_PMU_Get_CCNTR(); +} + +void perfc_port_clear_system_timer_ovf_pending(void) +{ + PMU->OVSCLR = PMU_OVSCLR_CYCCNT_STATUS_Msk; +} + +void perfc_port_stop_system_timer_counting(void) +{ + /* stop the system timer */ + PMU->CNTENCLR = PMU_CNTENCLR_CCNTR_ENABLE_Msk; +} + +void perfc_port_clear_system_timer_counter(void) +{ + /* clear the system timer counter */ + PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; +} + +#endif + + diff --git a/perfc_port_pmu.h b/perfc_port_pmu.h new file mode 100644 index 0000000..2962c1e --- /dev/null +++ b/perfc_port_pmu.h @@ -0,0 +1,131 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ + +#if __PERFC_USE_PMU_PORTING__ + +#include "cmsis_compiler.h" + +/*============================ MACROS ========================================*/ +/*============================ MACROFIED FUNCTIONS ===========================*/ +#define __cpu_perf__(__str, ...) \ + using( \ + struct { \ + uint64_t dwNoInstr; \ + uint64_t dwNoMemAccess; \ + uint64_t dwNoL1DCacheRefill; \ + int64_t lCycles; \ + uint32_t wInstrCalib; \ + uint32_t wMemAccessCalib; \ + float fCPI; \ + float fDCacheMissRate; \ + } __PERF_INFO__ = {0}, \ + ({ \ + __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \ + __PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count(); \ + __PERF_INFO__.wInstrCalib = perfc_pmu_get_instruction_count() \ + - __PERF_INFO__.dwNoInstr; \ + __PERF_INFO__.wMemAccessCalib = perfc_pmu_get_memory_access_count() \ + - __PERF_INFO__.dwNoMemAccess; \ + __PERF_INFO__.dwNoL1DCacheRefill \ + = perfc_pmu_get_L1_dcache_refill_count(); \ + __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count(); \ + __PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count(); \ + }), \ + ({ \ + __PERF_INFO__.dwNoInstr = perfc_pmu_get_instruction_count() \ + - __PERF_INFO__.dwNoInstr \ + - __PERF_INFO__.wInstrCalib; \ + __PERF_INFO__.dwNoMemAccess = perfc_pmu_get_memory_access_count() \ + - __PERF_INFO__.dwNoMemAccess \ + - __PERF_INFO__.wMemAccessCalib; \ + __PERF_INFO__.dwNoL1DCacheRefill \ + = perfc_pmu_get_L1_dcache_refill_count() \ + - __PERF_INFO__.dwNoL1DCacheRefill; \ + \ + __PERF_INFO__.fDCacheMissRate \ + = (float)( (double)__PERF_INFO__.dwNoL1DCacheRefill \ + / (double)__PERF_INFO__.dwNoMemAccess) \ + * 100.0f; \ + \ + __PERF_INFO__.fCPI = (float)( (double)__PERF_INFO__.lCycles \ + / (double)__PERF_INFO__.dwNoInstr); \ + if (__PLOOC_VA_NUM_ARGS(__VA_ARGS__) == 0) { \ + __perf_counter_printf__( "\r\n" \ + "[Report for " __str "]\r\n" \ + "-----------------------------------------\r\n" \ + "Instruction executed: %lld\r\n" \ + "Cycle Used: %lld\r\n" \ + "Cycles per Instructions: %3.3f \r\n\r\n" \ + "Memory Access Count: %lld\r\n" \ + "L1 DCache Refill Count: %lld\r\n" \ + "L1 DCache Miss Rate: %3.4f %% \r\n" \ + , \ + __PERF_INFO__.dwNoInstr, \ + __PERF_INFO__.lCycles, \ + (double)__PERF_INFO__.fCPI, \ + __PERF_INFO__.dwNoMemAccess, \ + __PERF_INFO__.dwNoL1DCacheRefill, \ + (double)__PERF_INFO__.fDCacheMissRate \ + ); \ + } else { \ + __VA_ARGS__ \ + } \ + })) \ + __cycleof__("", { __PERF_INFO__.lCycles = __cycle_count__; }) + + +/*============================ TYPES =========================================*/ +typedef uint32_t perfc_global_interrupt_status_t; + +/*============================ GLOBAL VARIABLES ==============================*/ +/*============================ LOCAL VARIABLES ===============================*/ +/*============================ PROTOTYPES ====================================*/ +extern +void perfc_port_pmu_insert_to_debug_monitor_handler(void); + +extern +uint64_t perfc_pmu_get_instruction_count(void); + +extern +uint64_t perfc_pmu_get_memory_access_count(void); + +extern +uint64_t perfc_pmu_get_L1_dcache_refill_count(void); + +/*============================ IMPLEMENTATION ================================*/ + +__STATIC_INLINE +perfc_global_interrupt_status_t perfc_port_disable_global_interrupt(void) +{ + perfc_global_interrupt_status_t tStatus = __get_PRIMASK(); + __disable_irq(); + + return tStatus; +} + +__STATIC_INLINE +void perfc_port_resume_global_interrupt(perfc_global_interrupt_status_t tStatus) +{ + __set_PRIMASK(tStatus); +} + + + + +#endif \ No newline at end of file diff --git a/systick_wrapper_gcc.S b/systick_wrapper_gcc.S index 382aebc..822d321 100644 --- a/systick_wrapper_gcc.S +++ b/systick_wrapper_gcc.S @@ -15,6 +15,7 @@ ;* * ;****************************************************************************/ +#if !__PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ .syntax unified .arch armv6-m @@ -28,7 +29,7 @@ __wrap_SysTick_Handler: push {r4, r5} push {r4, lr} - ldr R0, =user_code_insert_to_systick_handler + ldr R0, =perfc_port_insert_to_system_timer_insert_ovf_handler blx R0 pop {r4, r5} mov lr, r5 @@ -42,3 +43,4 @@ __wrap_SysTick_Handler: __ensure_systick_wrapper: bx lr +#endif \ No newline at end of file diff --git a/systick_wrapper_gnu.s b/systick_wrapper_gnu.s index ee2dbca..f7be081 100644 --- a/systick_wrapper_gnu.s +++ b/systick_wrapper_gnu.s @@ -14,34 +14,40 @@ ;* limitations under the License. * ;* * ;****************************************************************************/ +#if defined(_RTE_) +# include "RTE_Components.h" +#endif +#if !defined(__RTE_PERFC_PORTING_USER_DEFINED__) && !defined(__PERFC_USE_PMU_PORTING__) - .syntax unified - .arch armv6-m - +#if !__PERFC_CFG_DISABLE_DEFAULT_SYSTICK_PORTING__ + .syntax unified + .arch armv6-m .eabi_attribute Tag_ABI_align_preserved, 1 .text .thumb .thumb_func - .align 2 - .globl $Sub$$SysTick_Handler - .type $Sub$$SysTick_Handler, %function + .align 2 + .globl $Sub$$SysTick_Handler + .type $Sub$$SysTick_Handler, %function $Sub$$SysTick_Handler: push {r4, r5} push {r4, lr} - ldr R0, =user_code_insert_to_systick_handler + ldr R0, =perfc_port_insert_to_system_timer_insert_ovf_handler blx R0 pop {r4, r5} mov lr, r5 pop {r4, r5} ldr R0, =$Super$$SysTick_Handler bx R0 - - .globl __ensure_systick_wrapper - .type __ensure_systick_wrapper, %function + .globl __ensure_systick_wrapper + .type __ensure_systick_wrapper, %function __ensure_systick_wrapper: bx lr +#endif + +#endif \ No newline at end of file diff --git a/systick_wrapper_ual.s b/systick_wrapper_ual.s index 9e7b64a..63878cc 100644 --- a/systick_wrapper_ual.s +++ b/systick_wrapper_ual.s @@ -22,11 +22,11 @@ |$Sub$$SysTick_Handler| PROC EXPORT |$Sub$$SysTick_Handler| - IMPORT user_code_insert_to_systick_handler + IMPORT perfc_port_insert_to_system_timer_insert_ovf_handler IMPORT |$Super$$SysTick_Handler| push {r4, r5} push {r4, lr} - LDR R0, =user_code_insert_to_systick_handler + LDR R0, =perfc_port_insert_to_system_timer_insert_ovf_handler BLX R0 pop {r4, r5} mov lr, r5 diff --git a/template/perfc_port_user.c b/template/perfc_port_user.c new file mode 100644 index 0000000..a44f5fb --- /dev/null +++ b/template/perfc_port_user.c @@ -0,0 +1,132 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ +#undef __PERF_COUNT_PLATFORM_SPECIFIC_HEADER__ + +#include +#include +#include + +#define __IMPLEMENT_PERF_COUNTER +#include "perf_counter.h" + +#if defined(__IS_COMPILER_GCC__) +# pragma GCC diagnostic ignored "-Wattributes" +#endif + +#if defined(__clang__) +# pragma clang diagnostic ignored "-Wunknown-warning-option" +# pragma clang diagnostic ignored "-Wreserved-identifier" +# pragma clang diagnostic ignored "-Wconditional-uninitialized" +# pragma clang diagnostic ignored "-Wcast-align" +# pragma clang diagnostic ignored "-Wmissing-prototypes" +#endif + + +/*============================ MACROS ========================================*/ +/*============================ MACROFIED FUNCTIONS ===========================*/ +/*============================ TYPES =========================================*/ +/*============================ GLOBAL VARIABLES ==============================*/ +/*============================ LOCAL VARIABLES ===============================*/ +/*============================ PROTOTYPES ====================================*/ +/* low level interface for porting */ +extern +uint32_t perfc_port_get_system_timer_freq(void); +extern +int64_t perfc_port_get_system_timer_top(void); +extern +bool perfc_port_is_system_timer_ovf_pending(void); +extern +bool perfc_port_init_system_timer(bool bTimerOccupied); +extern +int64_t perfc_port_get_system_timer_elapsed(void); +extern +void perfc_port_clear_system_timer_ovf_pending(void); +extern +void perfc_port_stop_system_timer_counting(void); +extern +void perfc_port_clear_system_timer_counter(void); + +/*============================ IMPLEMENTATION ================================*/ +/*============================ INCLUDES ======================================*/ + +#if __PERFC_USE_USER_CUSTOM_PORTING__ + +bool perfc_port_init_system_timer(bool bIsTimeOccupied) +{ + bool bResult = true; + do { + if (bIsTimeOccupied) { + break; + } + + __IRQ_SAFE { + /* Configure the system timer count with the longest possible period + * clear counter + * Clear overflow pending flag + * Enable interrupt if required + * start counting + */ + } + } while(0); + + return true; +} + +uint32_t perfc_port_get_system_timer_freq(void) +{ + /* return the system timer frequency */ + return 0; +} + +bool perfc_port_is_system_timer_ovf_pending(void) +{ + /* whether the system timer overflow is pending */ + return false; +} + +int64_t perfc_port_get_system_timer_top(void) +{ + /* the top value of the counting */ + return 0; +} + +int64_t perfc_port_get_system_timer_elapsed(void) +{ + /* the elapsed count number since last overflow */ + return 0; +} + +void perfc_port_clear_system_timer_ovf_pending(void) +{ + /* clear the overflow pending flag */ +} + +void perfc_port_stop_system_timer_counting(void) +{ + /* stop the system timer */ +} + +void perfc_port_clear_system_timer_counter(void) +{ + /* clear the system timer counter */ +} + +#endif + + diff --git a/template/perfc_port_user.h b/template/perfc_port_user.h new file mode 100644 index 0000000..5cc8477 --- /dev/null +++ b/template/perfc_port_user.h @@ -0,0 +1,53 @@ +/**************************************************************************** +* Copyright 2024 Gorgon Meducer (Email:embedded_zhuoran@hotmail.com) * +* * +* Licensed under the Apache License, Version 2.0 (the "License"); * +* you may not use this file except in compliance with the License. * +* You may obtain a copy of the License at * +* * +* http://www.apache.org/licenses/LICENSE-2.0 * +* * +* Unless required by applicable law or agreed to in writing, software * +* distributed under the License is distributed on an "AS IS" BASIS, * +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * +* See the License for the specific language governing permissions and * +* limitations under the License. * +* * +****************************************************************************/ + +/*============================ INCLUDES ======================================*/ + +#if __PERFC_USE_USER_CUSTOM_PORTING__ + +/*============================ MACROS ========================================*/ +/*============================ MACROFIED FUNCTIONS ===========================*/ +/*============================ TYPES =========================================*/ +typedef uint32_t perfc_global_interrupt_status_t; + +/*============================ GLOBAL VARIABLES ==============================*/ +/*============================ LOCAL VARIABLES ===============================*/ +/*============================ PROTOTYPES ====================================*/ +/*============================ IMPLEMENTATION ================================*/ + +static +inline +perfc_global_interrupt_status_t perfc_port_disable_global_interrupt(void) +{ + perfc_global_interrupt_status_t tStatus; + + /* get global interrupt status */ + /* disable global interrupt */ + /* return the status */ + + return tStatus; + +} + +static +inline +void perfc_port_resume_global_interrupt(perfc_global_interrupt_status_t tStatus) +{ + /* resume the stored global interrupt status */ +} + +#endif \ No newline at end of file