Includes Eltangas minor fixes (Jan/20/2021)

JTAG2.cpp

@@ -155,7 +155,7 @@ void JTAG2::set_parameter() {
         PARAM_BAUD_RATE_VAL = (baud_rate)param_val;
         break;
       }
-      // else fall through (invalid baud rate)      
+      // else fall through (invalid baud rate)
     default:
       set_status(RSP_ILLEGAL_PARAMETER);
       return;
@@ -164,7 +164,7 @@ void JTAG2::set_parameter() {
 }
 
 void JTAG2::set_device_descriptor() {
-  flash_pagesize = *(uint16_t *) &packet.body[244];
+  flash_pagesize = packet.body[244] + 256*packet.body[245];
   eeprom_pagesize = packet.body[246];
   // Now they've told us what we're talking to, and we will try to connect to it
   /* Initialize or enable UPDI */
@@ -226,7 +226,7 @@ void JTAG2::enter_progmode() {
             DBG::debug('N', NVM_Status,NVM_Cmnd);
           }
         #endif
-        // Wait for completion of any previous NVM command then clear it with NOOP 
+        // Wait for completion of any previous NVM command then clear it with NOOP
         NVM_v2::wait<false>();
         UPDI::sts_b_l(NVM_v2::NVM_base + NVM_v2::STATUS, 0);
         NVM_v2::command<false>(NVM_v2::NOOP);
@@ -401,7 +401,7 @@ void JTAG2::erase() {
           NVM::command<false>(NVM::ER);
         }
       } else {
-        // Wait for completion of any previous NVM command then clear it with NOOP 
+        // Wait for completion of any previous NVM command then clear it with NOOP
         NVM_v2::wait<false>();
         NVM_v2::command<false>(NVM_v2::NOOP);
         // erase flash page
@@ -439,7 +439,7 @@ namespace {
 
   void NVM_v2_write (uint32_t address, uint16_t length, uint8_t write_cmd) {
     uint16_t current_byte_index = 10;         /* Index of the first byte to send inside the JTAG2 command body */
-    // Wait for completion of any previous NVM command then clear it with NOOP 
+    // Wait for completion of any previous NVM command then clear it with NOOP
     NVM_v2::wait<false>();
     NVM_v2::command<false>(NVM_v2::NOOP);
     // Send the write command
@@ -504,10 +504,10 @@ namespace {
     #endif
   }
 
-  
+
   void NVM_buffered_write(const uint16_t address, const uint16_t length, const uint8_t buff_size, const uint8_t write_cmnd) {
     uint8_t current_byte_index = 10;          /* Index of the first byte to send inside the JTAG2 command body */
-    uint16_t bytes_remaining = length;          /* number of bytes to write */
+    uint16_t bytes_remaining = length;        /* number of bytes to write */
 
     // Sends a block of bytes from the command body to memory, using the UPDI interface
     // On entry, the UPDI pointer must already point to the desired address

LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2018 Joao N. Rosa
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

NVM_v2.h

@@ -57,7 +57,7 @@ namespace NVM_v2 {
     EEMBER16    = 0x1C,    /* EEPROM 16-byte Erase Enable */
     EEMBER32    = 0x1D,    /* EEPROM 32-byte Erase Enable */
     CHER        = 0x20,    /* Erase Flash and EEPROM. EEPROM is skipped if EESAVE fuse is set. (UPDI access only.) */
-    EECHER      = 0x30    /* Erase EEPROM */
+    EECHER      = 0x30     /* Erase EEPROM */
   };
   // *** NVM Functions ***
   template <bool preserve_ptr>

README.md

@@ -33,7 +33,26 @@ Defaults: SpenceKonde jtag2updi: HV UPDI tool is disabled, Dlloydev jtag2updi: H
 
 ### [Wiki ...](https://github.com/Dlloydev/jtag2updi/wiki)
 
-For more designs, here's a great collection of AVR Programmers and Accessories:  [AVR-Programmer](https://github.com/wagiminator/AVR-Programmer)             
+For more designs, here's a great collection of AVR Programmers and Accessories:  [AVR-Programmer](https://github.com/wagiminator/AVR-Programmer) 
+
+## Change Log
+
+#### Version 1.0.0
+
+- Initial Version
+
+- Added MIT license text file (Jan/22/2021)
+
+- Includes Eltangas minor fixes (Jan/20/2021) 
+
+  ```
+  - Typos
+  - Redundant fossil copy/paste code removed
+  - Compilation warning fixed
+  ```
+
+- Unused pins are pulled up (Dec/5/2020)
+- Add define for HV UPDI programming (Dec/1/2020)       
 
 ------
 

UPDI_hi_lvl.cpp

@@ -13,42 +13,12 @@ bool UPDI::CPU_reset(){
     DBG::updi_reset();
   #endif
 
-  // Request reset
-  UPDI::stcs(UPDI::reg::ASI_Reset_Request, UPDI::RESET_ON);
-  // Release reset (System remains in reset state until released)
-  UPDI::stcs(UPDI::reg::ASI_Reset_Request, UPDI::RESET_OFF);
-
-  // Wait for the reset process to end.
-  // Either NVMPROG, UROWPROG or BOOTDONE bit will be set in the ASI_SYS_STATUS UPDI register.
-  // This indicates reset is complete.
-  #ifndef DISABLE_TARGET_TIMEOUT
-    uint8_t timeoutcount=0;
-    while ( UPDI::CPU_mode<0x0E>() == 0 && timeoutcount<2) //if it takes 200ms to come back after we release reset... it's never going to!
-    {
-      if (SYS::checkTimeouts() & WAIT_FOR_TARGET) {
-        SYS::clearTimeouts();
-        timeoutcount++;
-      }
-    }
-  #else
-    while ( UPDI::CPU_mode<0x0E>() == 0 );
-  #endif
-
-  #if defined(DEBUG_RESET) && !defined(DEBUG_LDCS)
-  //if LDCS is defined, it will pick this up
-  #ifndef DISABLE_TARGET_TIMEOUT
-  if(timeoutcount) {
-    DBG::debug('T',timeoutcount);
-  }
-  #endif
-  DBG::updi_post_reset(UPDI::CPU_mode<0xFF>());
-  #endif
-  #ifndef DISABLE_TARGET_TIMEOUT
-    return (timeoutcount<2); //if we didn't timeout and give up trying to bring it out of reset, return true
-  #else
-    return 1;
-  #endif
+  // Assert target reset
+  UPDI::CPU_reset_on();
+  // Deassert target reset and wait for target initialization
+  return UPDI::CPU_reset_off();
 }
+
 void UPDI::CPU_reset_on(){
   #if defined(DEBUG_RESET)
     DBG::updi_reset_on();
@@ -57,7 +27,6 @@ void UPDI::CPU_reset_on(){
   // Request reset
   UPDI::stcs(UPDI::reg::ASI_Reset_Request, UPDI::RESET_ON);
   // System remains in reset state until released
-
 }
 
 bool UPDI::CPU_reset_off(){
@@ -83,7 +52,7 @@ bool UPDI::CPU_reset_off(){
   #else
     while ( UPDI::CPU_mode<0x0E>() == 0 );
   #endif
-  
+
   #if defined(DEBUG_RESET) && !defined(DEBUG_LDCS)
   //if LDCS is defined, it will pick this up
   #ifndef DISABLE_TARGET_TIMEOUT

UPDI_lo_lvl.cpp

@@ -10,8 +10,8 @@
 #include "sys.h"
 #include "dbg.h"
 
-// _l  versions have long (24-bit) address poimter
-// otherwisem, address pointer is 16-bit
+// _l  versions have long (24-bit) address pointer
+// otherwise, address pointer is 16-bit
 
 
 
@@ -26,7 +26,6 @@ STCS - Store to Control Register
 
 */
 
-
 void UPDI::stcs(reg r, uint8_t data) {
 #ifdef DEBUG_STCS
   DBG::updi_stcs(r,data);
@@ -43,7 +42,6 @@ LDCS - Load Control Register
 
 */
 
-
 uint8_t UPDI::ldcs(reg r) {
 #ifdef DEBUG_LDCS
   DBG::updi_ldcs(r);
@@ -65,7 +63,6 @@ REP - Repeat Command
 
 */
 
-
 void UPDI::rep(uint8_t repeats) {
 #ifdef DEBUG_REP
   DBG::updi_rep(repeats);
@@ -158,8 +155,6 @@ STS - Byte oriented Store with Direct Addressing
 
 */
 
-
-
 void UPDI::sts_b(uint16_t address, uint8_t data) {
 #ifdef DEBUG_STS
   DBG::updi_sts(address,data);
@@ -230,7 +225,6 @@ STPTR - Set pointer for indirect addressing
 
 */
 
-
 void UPDI::stptr_b(uint8_t address) {
   // No debug code here - byte-addressed STPTR is never actually used!
   UPDI_io::put(UPDI::SYNCH);
@@ -262,7 +256,7 @@ void UPDI::stptr_l(uint32_t address) {
   UPDI_io::get();
 }
 
-void UPDI::stptr_p(uint8_t* addr_p, uint8_t n) {
+void UPDI::stptr_p(const uint8_t* addr_p, uint8_t n) {
   UPDI_io::put(UPDI::SYNCH);
   UPDI_io::put(0x68 + --n);
   UPDI_io::put(*(addr_p++));
@@ -279,7 +273,6 @@ LDPTR - Load pointer for indirect addressing
 
 */
 
-
 uint8_t UPDI::ldptr_b() {
   UPDI_io::put(UPDI::SYNCH);
   UPDI_io::put(0x28);
@@ -356,7 +349,7 @@ void UPDI::stinc_w(uint16_t data) {
 
 STINC noget variants
 For use when the RSD bit is set in control register A
-This is done to improve performance when doing busst writes
+This is done to improve performance when doing burst writes
 
 stinc_b_noget is copy of stinc_b without the get()
 

UPDI_lo_lvl.h

@@ -62,7 +62,7 @@ namespace UPDI {
   void stptr_b(uint8_t);
   void stptr_w(uint16_t);
   void stptr_l(uint32_t);
-  void stptr_p(uint8_t*, uint8_t);	// set address from selectable size address (1-3 bytes) via pointer to address
+  void stptr_p(const uint8_t*, uint8_t);  // set address from selectable size address (1-3 bytes) via pointer to address
 
   void st_b(uint8_t);
   void st_w(uint16_t);

jtag2updi.cpp

@@ -44,7 +44,6 @@ namespace {
 
   }
 
-
   inline void loop() {
     #if (defined(USE_HV_PROGRAMMING) && (defined(__AVR_ATmega328P__) || defined(__AVR_ATtiny_Zero_One__) || defined(__AVR_ATmega_Zero__) || defined(__AVR_DA__)))
     SYS::setPOWER();
@@ -194,5 +193,4 @@ namespace {
       }
     #endif
   }
-
 }