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V2k1 More minor typo fixes ("delimet" -> "delimit")
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DaveMcEwan committed Nov 10, 2023
1 parent 183d621 commit 85e0585
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Showing 3 changed files with 8 additions and 8 deletions.
8 changes: 4 additions & 4 deletions MANUAL.md
Original file line number Diff line number Diff line change
Expand Up @@ -5271,7 +5271,7 @@ endmodule
### Fail Example (1 of 3)
```systemverilog
module M;
for (genvar i=0; i < 10; i++) // No begin/end delimeters.
for (genvar i=0; i < 10; i++) // No begin/end delimiters.
assign a[i] = i;
endmodule
```
Expand Down Expand Up @@ -5357,7 +5357,7 @@ endmodule
### Fail Example (1 of 8)
```systemverilog
module M;
if (x) // No begin/end delimeters.
if (x) // No begin/end delimiters.
assign a = 0; // if condition.
else if (x) begin: l_def
assign a = 1;
Expand All @@ -5372,7 +5372,7 @@ endmodule
module M;
if (x) begin: l_abc
assign a = 0;
end else if (x) // No begin/end delimeters.
end else if (x) // No begin/end delimiters.
assign a = 1; // else-if condition.
else begin: l_hij
assign a = 2;
Expand All @@ -5385,7 +5385,7 @@ module M;
assign a = 0;
end else if (x) begin: l_def
assign a = 1;
end else // No begin/end delimeters.
end else // No begin/end delimiters.
assign a = 2; // else condition
endmodule
```
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2 changes: 1 addition & 1 deletion testcases/syntaxrules/fail/generate_for_with_label.sv
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
module M;
for (genvar i=0; i < 10; i++) // No begin/end delimeters.
for (genvar i=0; i < 10; i++) // No begin/end delimiters.
assign a[i] = i;
endmodule
////////////////////////////////////////////////////////////////////////////////
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6 changes: 3 additions & 3 deletions testcases/syntaxrules/fail/generate_if_with_label.sv
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
module M;
if (x) // No begin/end delimeters.
if (x) // No begin/end delimiters.
assign a = 0; // if condition.
else if (x) begin: l_def
assign a = 1;
Expand All @@ -11,7 +11,7 @@ endmodule
module M;
if (x) begin: l_abc
assign a = 0;
end else if (x) // No begin/end delimeters.
end else if (x) // No begin/end delimiters.
assign a = 1; // else-if condition.
else begin: l_hij
assign a = 2;
Expand All @@ -24,7 +24,7 @@ module M;
assign a = 0;
end else if (x) begin: l_def
assign a = 1;
end else // No begin/end delimeters.
end else // No begin/end delimiters.
assign a = 2; // else condition
endmodule
////////////////////////////////////////////////////////////////////////////////
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