Update Derecho Port

[apcraig]

PR checklist

• Short (1 sentence) summary of your PR:
  Update Derecho port
• Developer(s):
  apcraig
• Suggest PR reviewers from list in the column to the right.
• Please copy the PR test results link or provide a summary of testing completed below.
  Full test suite run on derecho with 6 compilers. Tests pass as expected. Inteloneapi was added as a new supported compiler. Intel, cray, nvhpc were updated. Cray and nvhpc change answers. https://github.com/CICE-Consortium/Test-Results/wiki/cice_by_hash_forks#d9d0176ad7f4464116c3f17aa71e33da9e5fd921
• How much do the PR code changes differ from the unmodified code?
  • bit for bit for intel, gnu, intelclassic
  • different at roundoff level for cray, nvhpc
  • more substantial
• Does this PR create or have dependencies on Icepack or any other models?
  • Yes
  • No
• Does this PR update the Icepack submodule? If so, the Icepack submodule must point to a hash on Icepack's main branch.
  • Yes
  • No
• Does this PR add any new test cases?
  • Yes
  • No
• Is the documentation being updated? ("Documentation" includes information on the wiki or in the .rst files from doc/source/, which are used to create the online technical docs at https://readthedocs.org/projects/cice-consortium-cice/. A test build of the technical docs will be performed as part of the PR testing.)
  • Yes
  • No, does the documentation need to be updated at a later time?
    • Yes
    • No
• Please document the changes in detail, including why the changes are made. This will become part of the PR commit log.

Update derecho port

• update inteloneapi, validate, use -O1, problems with -check all.
• update cray to ncarenv/23.09 and cce/16.0.1, answers change
• update intel to ncarenv/23.09 and intel/2023.2.1, answer bit-for-bit
• update nvhpc to ncarenv/23.09 and nvhpc/23.7, answers change
• update queue so smaller jobs go into develop (shared) instead of main

Add ifndef __INTEL_LLVM_COMPILER (for intel oneapi) around an OMP loop that the compiler doesn't handle properly (reported to intel) in ice_history.F90.

Update QC documentation in the user guide to clarify where/how to run the cice.t-test.py script.