cpum.stx

Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to D:/verilog/cpu/xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Parameter xsthdpdir set to D:/verilog/cpu/xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Reading design: cpum.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file "D:\verilog\cpu\cpum.v" into library work
Parsing module <cpum>.
WARNING:HDLCompiler:1335 - "D:\verilog\cpu\cpum.v" Line 4: Port ins must not be declared to be an array
ERROR:HDLCompiler:329 - "D:\verilog\cpu\cpum.v" Line 46: Target <ra> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "D:\verilog\cpu\cpum.v" Line 47: Target <rb> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "D:\verilog\cpu\cpum.v" Line 48: Target <rc> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:329 - "D:\verilog\cpu\cpum.v" Line 49: Target <rd> of concurrent assignment or output port connection should be a net type.
ERROR:HDLCompiler:598 - "D:\verilog\cpu\cpum.v" Line 2: Module <cpum> ignored due to previous errors.
Verilog file D:\verilog\cpu\cpum.v ignored due to errors
--> 

Total memory usage is 4479492 kilobytes

Number of errors   :    5 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)