Skip to content
View Archfx's full-sized avatar
:octocat:
0xde5c1b13
:octocat:
0xde5c1b13

Highlights

  • Pro

Block or report Archfx

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Archfx/README.md

Hello World! [1] 

I am a Hardware and Firmware Design and Verification Engineer. My interests lie at the thin intersection of Electronics Engineering and Computer Science Engineering. ✌️

GitHub Twitter Twitter ORCiD LinkedIn ResearchGate Google Scholar dblp Insta Blog Website

[1] 0x48 0x65 0x6C 0x6C 0x6F 0x20 0x57 0x6F 0x72 0x6C 0x64 0x21

Pinned Loading

  1. FPGA-stereo-Camera-Basys3 FPGA-stereo-Camera-Basys3 Public

    Integration of two camera 📷 modules to Basys 3 FPGA

    Verilog 33 8

  2. sweetRV sweetRV Public

    sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA

    C++ 4 1

  3. RTK-NTRIP-RTCM RTK-NTRIP-RTCM Public

    Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.

    Python 28 6

  4. duo-de duo-de Public

    Surface Duo Dual Experience ( 🍰 AOSP | Android 15 | DUO1 | DUO2 )

    Shell 100 2

  5. FPGA-DepthMap-Basys3 FPGA-DepthMap-Basys3 Public

    Real Time depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.

    VHDL 14 4

  6. ice40lib ice40lib Public

    Peripheral library 📚 for open source FPGAs based on iCE40. (Configured for ICESugar-Nano)

    Verilog 5